clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<develonepi3> mmicko ZipCPU recommended that I ask you. I was able to build icestorm 8cac6c5840 with Yocto cross compiling for ARM on x86_64, but was seeing QA errors. They don't recommend installing in /usr/local/. I pulled the latest ver and now missing binary operator before token "(" 133 | #if __HAVE_FLOAT16 && __GLIBC_USE (IEC_60559_TYPES_EXT). Any idea?
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<gromero> hi
<gromero> I'm getting a syntax error like: ERROR: syntax error, unexpected TOK_REG, expecting TOK_ID
<gromero> but it do can synthesize the .v file without any error
<gromero> any clue on what exactly the parser is requesting there?
<daveshah> "bit" is a SystemVerilog keyword
<gromero> oh!
<gromero> daveshah: thanks a lot. indeed :)
<gromero> so it means that for simulation ir's a SystemVerilog parser and for synthesis it's only the synthesizable subset of Verilog?
<gromero> s/ir's/it's/
<daveshah> Yosys doesn't do significant simulation in the traditional sense, any sim it does do goes through the same elaboration/synth
<daveshah> It supports a subset of SystemVerilog features. bit as an alias for reg is one of them.
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<ZirconiumX> Well, cxxrtl makes it look a lot like Verilator
<gromero> daveshah: hrm but if it do goes through the same elaboration/synth, why the problematic code I've pasted do really synthetizes fine?
<daveshah> ZirconiumX: Yes that's why I said traditional sense - in the context of parsing
<daveshah> gromero: but it doesn't you said there was an error
<ZirconiumX> gromero: AIUI your code should parse fine without -sv
<ZirconiumX> You're not using anything actually SV in there
<daveshah> Indeed, the problem is nothing to do with simulation or synthesis but SystemVerilog vs Verilog
<gromero> ZirconiumX: daveshah ah got it. thanks :)
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