clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<promach3> Is it possible to simulate and synthesize and generate bitstream from https://github.com/aws/aws-fpga/blob/master/hdk/common/shell_v04261818/design/sh_ddr/sim/sh_ddr.sv ?
<tpb> Title: aws-fpga/sh_ddr.sv at master · aws/aws-fpga · GitHub (at github.com)
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<rjeli> hello! got an icebreaker @ ccc yesterday & in love
<rjeli> y’all are amazing, foss fpga is amazing
<OK_b00m3r> rjeli: o/
<ZipCPU> o/
<klotz> Yeah got one as well
<klotz> Hands down my best investment this year
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<meawoppl> Alright, I have another strange bug to report
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<meawoppl> rather I don't know if it is a bug or verilog "feature"
<meawoppl> yosys appears to support synthesizing case statements where the labels aren't defined
<meawoppl> localparam[3:0] START = 0, FRAME_START = 1, FRAME_END = 2, IGNORE = 3, LONGPACKET = 4, UNKNOWN = 10, DONE = 15; reg[3:0] state = START;
<meawoppl> case(state)
<meawoppl> FOO: whatever
<meawoppl> endcase
<meawoppl> compiles
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<daveshah> I think this is a Verilog oddity
<daveshah> case statements allow signals as labels
<daveshah> and undefined signals default to a 1 bit wire (without `default_nettype)
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<daveshah> You should at least get a warning like `Warning: Identifier `\FOO' is implicitly declared.`
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<meawoppl> oui, that seems fraught imho, signals as labels seems a little generally hairy, but I can see how it could be used....
<meawoppl> is there any way to have yosys promote warnings to errors?
<meawoppl> My general experience there is that warnings are more likely than not errors of some variety
<meawoppl> (but as advertised, I am a verilog n00b)
<meawoppl> Also I feel like I should send you a bottle of whisky for how helpful you have been daveshah
<daveshah> You can do ` -e regex` to turn warnings matching a regex into an error
<daveshah> In this case the best option is to add "`default_nettype none" at the top of your file
<daveshah> This will prevent any implicit signals from being created
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<devik2> ZipCPU, can I ask about your f_past_valid usage ?
<ZipCPU> Sure, what's your question?
<devik2> what's difference from $initstate ?
<ZipCPU> Probably just that I've never used $initstate ;)
<ZipCPU> But seriously, I'd need to look it up to know
<devik2> ahh .. I started to learn from your blog and I then found this one and it seems to do the same :-)
<devik2> btw, I tried to understand how to verify whole simple MCU, I just created extra simple one as one case() - all in one cycle, no pipelining,
<ZipCPU> Ok, go on
<devik2> then fully pipelined one with bypasses etc..
<devik2> and proved they have the same output for any input code (coded as $anyconst)
<ZipCPU> I should point out ... I'm still very much the learner myself. I've only been doing formal types of stuffs since ... October, 2017
<devik2> it seems to work, I proved it for 20 cycles and any 8 instruction code
<ZipCPU> Awesome! How about induction?
<devik2> not yet :-(
<devik2> I think, is ever possible to do sequntioal equivalence as induction ?
<devik2> it seems as too complex task
<ZipCPU> Might depend upon the core
<devik2> interestingly, yosys "sat" command is sometimes faster in proving than yosys-smt
<ZipCPU> Sorry, but .... I'm going to need to step away here. Perhaps we can continue later?
<devik2> yeah that ok,
<devik2> I have to ho to sleep, it is 23PM here
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