clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<ZirconiumX> So, for the $alu cell, what would be a cell that would change BI at runtime as opposed to it being constant?
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<ZirconiumX> daveshah, maybe?
<daveshah> Hypothetically an adder/subtractor
<daveshah> I don't know if Yosys maps these yet (from add sub and mux)
<daveshah> But it's something I've wanted to look at at some point
<ZirconiumX> I'm wondering if trying to specialise based on CI and/or BI is worth it or not
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<daveshah> BI=1 is a common case (subtractor)
<daveshah> Fixed BI and CI is much more common than variable
<ZirconiumX> I've been inspecting the output of Quartus and it's interesting (to me) that comparisons are not done with carry chains
<ZirconiumX> Which is actually probably cmp2lut
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<daveshah> Not just cmp2lut, we should probably have a mode in Yosys not to convert any compare to soft logic
<mwk> tbh I think we shouldcompletely dump convering compares to sub
<mwk> it's completely bonkers
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<daveshah> Agreed
<daveshah> If nothing else because it prevents any serious downstream optimisation
<mwk> well it's also horribly inefficient
<mwk> at least on xilinx
<mwk> you could reduce area 2× by using the carry chain in a better way for the variable inputs case (two pairs of input bits per LUT)
<mwk> and at least 5× when one of the inputs is const
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