clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<ZirconiumX> So, I've been adding asynchronous set for synth_intel_alm, and now Yosys is spewing "Warning: Complex async reset for dff '\Q'."
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<tpb> Title: dff_sim.v · GitHub (at gist.github.com)
<daveshah> Yes, that's a standard warning for DFF with both set and clear
<daveshah> They are usually not implementable, although it seems Intel is an exception
<tpb> Title: DFFEAS Primitive (at www.intel.com)
<ZirconiumX> This is my reference here
<mwk> intel and old xilinx
<mwk> I have that issue on my TODO list for that reason
<mwk> yosys will warn you, but will make the right-ish cell anyway, except
<mwk> 1) it ignores the priority of the reset/set on input and always assumes priority of reset over set (which is what most vendors pick anyway, I think)
<mwk> 2) it will emit dumb redundant logic on the set input
<ZirconiumX> 1) holds for Intel, judging by the truth table
<mwk> so... ignore the warning, I'll fix it sooner or later
<ZirconiumX> Noted
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<ZirconiumX> ...Would it be better to use asynchronous load over async reset/set?
<ZirconiumX> Since now I have async reset/set, and async load/data
<ZirconiumX> Which is effectively a duplicate
<mwk> not really a duplicate, reset/set is strictly better
<mwk> if you try to implement async set/reset in terms of async load, it's too easy to end up in glitchland
<mwk> also, it may be a good idea to use both and save some logic
<mwk> $_DLATCHSR_* maps cleanly to async load/data + async reset + async set
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<mwk> (yosys doesn't emit them at this point, but that's *also* on my list)
<daveshah> ECP5 actually has async load too, but it's totally unused by the vendor tools (unless you create an ncl file)
<ZirconiumX> Okay, fair
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