clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<mkurc> Hello, I have a question: What is the best way to detect in techmap that a particular input port of the cell is unconnected?
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<ZirconiumX> mkurc: probably by using CONSTMSK and CONSTVAL
<ZirconiumX> Because unconnected ports are effectively constant 'bx
<pepijndevos> There is a way to make yosys make a truth table for a combinational circuit right? I forgot how...
<daveshah> pepijndevos: eval
<mkurc> ZirconiumX: My current observation is that a port is unconnected when CONSTMSK == 0 and CONSTVAL == 0
<ZirconiumX> mkurc: That's incorrect
<ZirconiumX> `help techmap` shows that it should be CONSTMSK == 1 and CONSTVAL == 'bx
<ZirconiumX> What you have there is not a constant
<pepijndevos> daveshah, it doesn't like me: Failed to evaluate signal \R10C7_S13 at { \R1C16_W81 \R1C5_E26 } = 2'00: Missing value for \R10C7_S13.
<daveshah> Haven't seen that before but I guess it's because you have an input that isn't set or in the list of truth table signals?
<pepijndevos> Hum, I did flatten and now it's happy
<mkurc> ZirconiumX: But that does not work for me. CONSTVAL is never equal to 'bx. I tried both with '==' and '===' comparison operators.
<ZirconiumX> Well, first off, what are you trying to do?
<ZirconiumX> As in, why do you need to check if something is disconnected?
<pepijndevos> daveshah, how do carry chains work on ECP5?
<mkurc> ZirconiumX: Let's say that I have a cell representing a PLL and it has a RST input.
<mkurc> ZirconiumX: I'm writing a techmap for it that will transform it to another representation of the PLL. And I want to detect whether the RST input is connected. Because if it is not then I need to force it to eg. logic 1 in the cell that I'm mapping to.
<ZirconiumX> But then, why not have something like `assign reset_val = (input_reset === 1'b0) ? 1'b0 : 1'b1;`?
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<mkurc> ZirconiumX: That would work provided that I can assume that an unconnected port is tied to 0. But what if I want to force RST to 0 then? It'll be forced to 1.
<ZirconiumX> An unconnected port is not tied to zero
<ZirconiumX> It's tied to 'bx
<ZirconiumX> If input_reset is 1, that returns 1
<ZirconiumX> If input_reset is 0, that returns 0
<ZirconiumX> If input_reset is x, that returns 1
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<mmicko> hi develonepi3, just use make PREFIX=/opt install and it should be fine, that way you will get binaries in /opt/bin, maybe that is not best option for it but you can use any prefix that is fine for your envrionment
<mmicko> and sorry for late reply, was afk, thanks ZipCPU for letting me know
<develonepi3> mmicko thanks will try it !
<mmicko> if you need some guidelines, you can check scripts at https://github.com/mmicko/cross-fpga/tree/master/scripts but those are for making static binaries and some tools lack some of features due to that
<tpb> Title: cross-fpga/scripts at master · mmicko/cross-fpga · GitHub (at github.com)
<develonepi3> mmicko That helped was able to get the package built. And now having some QA issues. This is a fork with chg'ed made in conf.mk /usr/local to /opt "https://github.com/develone/icestorm"
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<mmicko> develonepi3: there should be no need to change existing file, since you can overwrite them in build script, so if you are doing packaging for yocto, you actually need to call make from there and then can set PREFIX parameter, in project itself usual default value is left to cover most users
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