clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<bobzoidting> I have a question about synthesis in general , probably not specific to yosys. Is it best practice to try and minimize the number of states in a statemachine or not? Will adding states instead of using combinational logic within states increase the logic size?
<bobzoidting> One example is, lets' say I have a statemachine to serialize RGB colours in 8bit/8bit/8bit format onto a serial bus for LEDs, does it make sense to separate these out the colours into states. I.E a Red colour state, Green colour state or Blue colour state
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<janrinze> daveshah: ABC: Warning: AIG with boxes has internal fanout in 0 complex flops and 1 carries. What does this mean?
<daveshah> It's just an ABC thing
<daveshah> I think it means a connection between a carry chain and other logic
<daveshah> It's not actually a problem of any kind, I don't know why it's a warning and not just a message
<janrinze> daveshah: thanks. the design works well, no issues.
<janrinze> daveshah: I've just added a floating point copro to my cpu. was quite a bit of fiddling to get it right but it works now. It still surprises me how well Yosys can convert complex verilog statements into something that runs quite fast.
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<bobzoidting> It's pretty cool how much you can do now with free toolchains
<bobzoidting> and for $10 you can build a custom RISCV MCU in a few hours with a custom peripheral
<janrinze> bobzoidting: Indeed. And the tools get better every day.
<bobzoidting> yeah, free RISCV implementations with free synthesis tools and free compilers..You can do so much so easily
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