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<pepijndevos>
Why is there a $PACKER_VCC and $PACKER_GND in my Nextpnr generic output? They got mapped to a slice with a LUT INIT of 1 and 0, as integers, while all other LUT have binary strings as init.
<daveshah>
They are for driving 0 and 1 as needed
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<pepijndevos>
daveshah, right, but on Gowin ther is just a global VCC and VSS net, can I express that somehow?
<daveshah>
You could modify the packer to create a single cell with two pins instead, one for the Vcc net and one for the Vss net
<daveshah>
and use that instead of the LUTs
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<pepijndevos>
omg, I can make a Gowin bitstream! I just need to add constraints. Does the generic target have a way to do that? I can probably find this...
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<daveshah>
pepijndevos: you can either manually instantiate IO buffers and set the BEL attribute on them; or hack something in Python to set the BEL attribute on cells
<daveshah>
I would recommend the former
<pepijndevos>
Hm okay, but how does that interact with reading a netlist?
<daveshah>
Effectively, don't have any top level ports in your netlist
<daveshah>
Just IO buffer cells instantiated with the BEL=... and keep=1 attributes set
<daveshah>
I have an example somewhere, let me dig it out
<daveshah>
This is for Xilinx but same principle applies elsewhere
<daveshah>
(you would need blackbox definitions for the IO buffer primitives too)
<pepijndevos>
Oh! On the verilog side. Interesting.
<pepijndevos>
Nice, thanks
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<janrinze>
will 'autoname' add more comprehension for ecp5 too?
<janrinze>
i see it's added for synt_ice40 but it could easily be added to synth_ecp5 too, right?
<janrinze>
i just answered my own question. Added the run("autoname"); to the if (check_label("check")) and apparently it works okay.
<janrinze>
Also give a lot more sensible info about the critical path now. Nice.
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<daveshah>
janrinze: yeah
<daveshah>
I'll apply that now
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<daveshah>
janrinze: done
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<janrinze>
daveshah: can we improve the memory implementation? somehow it's near impossible to have a large dual port memory inferred. I have a solution that works with manually setting up lots of DP16KD but initializing that with a file is quite a challenge.
<daveshah>
It needs a total rewrite and that's a big project
<janrinze>
hmm.. it does?
<janrinze>
What if we do things incrementally?
<ZirconiumX>
daveshah: it's the memory_bram pass, right?
<daveshah>
Yeah, don't even look at the code
<daveshah>
It has been the source of several horrible synthesis bugs too
<janrinze>
It is possible to have MemoryA correctly inferrred with DP16KD.
<janrinze>
Thus we can inferr two seperate memory blocks with DP16KD. which are unrelated.
<janrinze>
now if we use the access ports of the second and tie them to the first, discarding the second blocks, we should have a working DPRAM
<janrinze>
right?
<janrinze>
Or does the default implementation use both ports?
<janrinze>
if the address for reading and writing of memA uses the same wires we can guarantee that only one port is sufficient.
<janrinze>
thus implying that if the same is true for memB we can safely assume that each can be mapped to a single port of the DP16KD respectively.
<janrinze>
Right?
<daveshah>
This is all technically correct
<daveshah>
But memory_bram is a hacky enough pass already
<janrinze>
I can feel a big "But..." coming..
<daveshah>
And personally I'm not interested in adding any more hackyness or time wasting missynthesis bugs to a pass that really needs reconsideration
<janrinze>
makes sense.
<daveshah>
Particularly given there are several other missing features like async bram, a better transparency model and resets
<daveshah>
Better handling of transparent ports, in particular, is needed for support for common dpram patterns
<janrinze>
Okay, understood.
<janrinze>
Since i already have a module written to use DP16KD directly, I would like to find a way to set it up using initial $readmemh("rom_memory.hex",memory);
<janrinze>
because I am pretty sure that this readmemh wont work on a module. :-D