clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<promach> ERROR: timing analysis failed due to presence of combinatorial loops, incomplete specification of timing ports, etc.
<promach> yosys does not give me loop warnings
<promach> so, what really causes this error ?
<promach> ok, found what causes the error :)
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<pepijndevos> How can I tell yosys not to do assign {foo, bar, baz} = {a, b, c}?
<pepijndevos> I did splitnets but it still uses some arrays
<pepijndevos> It's actually doing assign { gen_043_, gen_042_, gen_041_, gen_040_, gen_039_, gen_038_, gen_037_, gen_036_ } = { \ctr[25] , \ctr[24] , \ctr[23] , \ctr[22] , \ctr[21] , \ctr[20] , \ctr[19] , \ctr[18] };
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<ZirconiumX> pepijndevos: But why? This is, after all, entirely valid Verilog semantics
<pepijndevos> ZirconiumX, but not Verilog that the Gowin floorplanner understands.
<pepijndevos> It only deals with a very limited subset of post-synth Verilog
<ZirconiumX> Hmm, write_verilog stuff like this might be one for whitequark?
<daveshah> This is a known issue, see https://github.com/YosysHQ/yosys/issues/1286
<tpb> Title: Yosys emits assigns with a concatenated expression on the LHS · Issue #1286 · YosysHQ/yosys · GitHub (at github.com)
<daveshah> Unfortunately structural Verilog isn't well defined
<ZirconiumX> So yeah, have fun pepijndevos
<ZirconiumX> :P
<pepijndevos> I love fun
<cr1901_modern> Issue #1286 came up in omigen... ISTR that this is _not_ valid Verilog
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<daveshah> cr1901_modern: it definitely is
<daveshah> (from 1364-2005 p70)
<daveshah> the question is whether it is "valid" structural Verilog, but I don't think structural Verilog is actually a defined thing
<cr1901_modern> that's the sysverilog spec?
<daveshah> No, Verilog 2005
<daveshah> I don't think it's a new feature
<daveshah> let me check 01
<cr1901_modern> Okay, I'm wrong then. Well, ISE doesn't accept that either
<daveshah> Yeah, same example appears in 2001 too
<daveshah> I'm surprised by that, it's quite a common pattern
<cr1901_modern> That being said, note that your example is {a, b} = c + d + e;
<cr1901_modern> ISE doesn't accept {a, b} = {c, d};
<cr1901_modern> i.e. I think the destructuring on both sides is what it doesn't like
<daveshah> That's even stranger
<ZirconiumX> mwk: Why on earth did you decide to reverse engineer such a cursed compiler?
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<FSM_Dude> Hey! Is there anyway here who develops/runs Yosys on a MacBook?
<daveshah> It's definitely something some people do, don't think any of the core devs use macos though
<FSM_Dude> Okay! I'm running into a problem since I updated Xcode / MacOS
<FSM_Dude> I just ran make clean, and rebuilding everything to see if it might solve the issue
<ZirconiumX> At risk of being snarky, it's difficult to help solve "problems"
<FSM_Dude> I understand! I actually wanted to ask for help, then thought: maybe cleaning and rebuilding helps
<ZirconiumX> Sure, but we still don't know what your problem is
<FSM_Dude> If the problem persists, I'll let you guys know, and give a somewhat broader explanation what exactly goes wrong :)
<FSM_Dude> Well, basically, when I ran fsm_recode -encoding binary, I get a Thread_Bad_Access
<FSM_Dude> and then Yosys stops
<ZirconiumX> This is already a lot more helpful
<ZirconiumX> Can you post your code somewhere?
<daveshah> If you don't get to the bottom of it quickly, running with valgrind (if that exists on osx) is often handy for this kind of thing
<ZirconiumX> I think Valgrind has support for OS X
<FSM_Dude> Cool, Ill look into it!
<FSM_Dude> After rebuilding it still happens
<FSM_Dude> I didn't change any code here
<daveshah> It's possible that some latent bug has been triggered by a compiler/stdlib update
<ZirconiumX> It wouldn't be the first bug we've had with fsm.
<FSM_Dude> The Thread_Bad_Access seems to happen in register.cc
<FSM_Dude> in Pass::call(RTLIL::Design *design, std::vector<std::string> args)
<FSM_Dude> I'm fairly new to C++ and Yosys, so sorry for need being of great help...
<ZirconiumX> Which line?
<ZirconiumX> It'll say something like "register.cc:XXX"
<mwk> ZirconiumX: well if it wasn't that cursed, I could perhaps actually use it instead of reversing it
<ZirconiumX> ...You have a point
<FSM_Dude> line number 294 : pass_register[args[0]]->execute(args, design);
<FSM_Dude> For now I guess, Ill switch to my linux machine :P
<mwk> FSM_Dude: could you give us the verilog / ilang code that triggers the bug?
<FSM_Dude> Can I post it all here?
<FSM_Dude> Or how do I get the Verilog to you guys
<ZirconiumX> Copy and paste it to gist.github.com
<ZirconiumX> Don't paste it into IRC; it will be very spammy and difficult to use
<FSM_Dude> Okay
<FSM_Dude> Mind you, it's not my verilog code. Im a student trying to run a set of verilog benchmarks. I'm interested in building new state encoding techniques into Yosys and analyse the outcomes
<FSM_Dude> To analyse, I use a set of benchmark verilog files :)
<ZirconiumX> Sure, but anything that takes in Verilog is inevitably going to crash somewhere
<FSM_Dude> It's a shiftreg I think
<FSM_Dude> I gtg now, Im on my laptop gonna get to my linux machine at home
<ZirconiumX> ...It works under WSL
<FSM_Dude> WSL?
<ZirconiumX> Windows Subsystem for Linux
<FSM_Dude> the fsm_recode -encoding binary?
<ZirconiumX> Yep
<FSM_Dude> Guess it's Xcode/OSx specific?
<ZirconiumX> What's your full Yosys command line?
<FSM_Dude> Thanks for testing tho! I'll switch to linux then
<ZirconiumX> Sadly we can't fix the bug if you do
<FSM_Dude> Thats what I run
<FSM_Dude> in the Yosys shell
<ZirconiumX> That script works too
<FSM_Dude> Hmm
<FSM_Dude> Before I updated my OSx and Xcode everything worked. So I guess it has to do with that change
<ZirconiumX> Possibly. That still suggests there's a latent bug *somewhere*
<FSM_Dude> How can I investigate this better/be of help to you guys
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<ZirconiumX> Funnily enough, Yosys has a command for finding bugs
<ZirconiumX> So, I presume you have that script in a file somewhere?
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<FSM_Dude> I type every command in the shell most of the times
<ZirconiumX> You should put it in a script
<ZirconiumX> And then use `yosys -s script.ys`
<FSM_Dude> Okay, thanks!
<ZirconiumX> Does that still crash with the segfault?
<FSM_Dude> Yes
<ZirconiumX> Right, so now I want you to run `yosys -p "bugpoint -clean -script script.ys; write_ilang testcase.il" your_verilog_file.v`
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<FSM_Dude> autoidx 3
<FSM_Dude> is in both .il files
<FSM_Dude> I gtg now, got classes. I'll come back to you! Let's try to fix it :)
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