clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<ZipCPU> pepijndevos[m]: Synchronization with a (slow) digital stream should be easy. 1) Matched filter (boxcar should work nicely), 2) multiply data with itself delayed by a half a bit (just xor the MSBs), 3) run a PLL on the result
<tpb> Title: Building a Simple Logic PLL (at zipcpu.com)
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<pepijndevos> ZipCPU, Interesting, I'll read it later. This is what I have now: https://github.com/pepijndevos/vhdlwire/blob/master/src/receiver.vhd#L107
<tpb> Title: vhdlwire/receiver.vhd at master · pepijndevos/vhdlwire · GitHub (at github.com)
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<ZipCPU> Do you understand how that algorithm works?
<pepijndevos> ZipCPU, uuhhh, kinda
<ZipCPU> <smiles boardly>
<ZipCPU> *broadly
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<pepijndevos> ??
<pepijndevos> It's way past bedtime over here, but will happily talk RF stuff tomorrow
<ZipCPU> It might take more time than IRC can give it
<ZipCPU> Thanks for posting it, though. It really helps me to understand what you are working with
<pepijndevos> (at the top is also links the C source, but I think I shared that already)
<ZipCPU> I think I can get a quick grasp for how it's working just from that alone
<ZipCPU> (I don't remember seeing it before ...)
<ZipCPU> Ouch ... that replacement must've been quite painful
<pepijndevos> It's basically a *very* crude PLL that counts a bit faster or slower if a transition happens before or after it expects it.
<pepijndevos> What I don't get... is how it rejects spurious transitions.... but maybe it just doesnt
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