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<pepijndevos>
Which operations does $alu implement? It seems just addition and subtraction?
<pepijndevos>
A building block supporting both binary addition/subtraction operations, and
<pepijndevos>
indirectly, comparison operations.
<whitequark>
yes
<pepijndevos>
indirectly?? Meaning it wraps a subtract in some logic to do comparison?
<whitequark>
I think so yes
<pepijndevos>
What I also don't get is the X output which always just seems to be the XOR of the inputs
<whitequark>
yes, that's what it is
<whitequark>
take a look at the circuit for a full adder
<pepijndevos>
But is there any case where this XOR is actually part of the adder hardware? At least in all implementations I've seen it's literally an XOR, not part of the vendor ALU primitive.
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<whitequark>
no idea
<pepijndevos>
ok
<whitequark>
not on FPGAs for sure
<pepijndevos>
Actually, I'm not sure what you mean with the full adder, because the ALU already has a carry in and carry out too, right?
<mwk>
pepijndevos: I don't think I understand your question really
<mwk>
the thing about FPGAs is, they don't really have alu cells
<mwk>
(except the ones in DSP slices, but they're a completely different thing)
<pepijndevos>
Right, just a LUT with a hardware carry
<mwk>
what FPGAs really do is reuse as much of the LUT as possible, and have the bare minimum of special carry chain logic
<mwk>
and maybe an extra XOR gate (for xilinx)
<pepijndevos>
hmmm okay
<pepijndevos>
So what I'm thinking about is... the Gowin ALU supports special comparison modes, but there does not seem to be a straightforward way to map an $alu cell to them as the comparison is "indirect"
<daveshah>
Realistically they'll be just setting the LUT init to some value
<pepijndevos>
Right, but if Yosys just sets them to add/sub and then wraps extra logic around them for comparison, it could be less than ideal I suppose.
<daveshah>
I would be careful creating too much hard logic for comparison as it might prevent optimisation down the line
<pepijndevos>
But then, IIRC I did not actually manage to make the vendor tools issue some of these modes, so maybe they are actually the same LUT contents.
<daveshah>
Older Lattice FPGAs had these modes too
<daveshah>
But they definitely didn't have any special hardware behind them beyond the LUT and carry logic
<pepijndevos>
Right
<mwk>
heh
<mwk>
$lt/$gt could actually be implemented in real clever ways on xilinx
<mwk>
using the carry chain
<mwk>
too bad we don't do it
<mwk>
right :(
<lukego>
Added the yosys "show" GUI dependencies to the nixpkgs package if anybody is interested. was a little fiddly with icons. as a separate package to avoid pulling it all in with the compiler. https://github.com/NixOS/nixpkgs/pull/73856
<tpb>
Title: yosys-withGui: New wrapper derivation with GUI runtime dependencies by lukego · Pull Request #73856 · NixOS/nixpkgs · GitHub (at github.com)
<lukego>
newbie alert: How do I make a ROM at the RTLIL level? I feel like $memrd is the right primitive but I don't see how to supply an initial value.
<daveshah>
They might have been improved since the 0.9 release, when that was probably generated
<lukego>
Is there a good place to look for RTLIL examples to help interpret the docs? Or source is the best bet?
<daveshah>
Write some Verilog and look at the RTLIL it produces
<lukego>
I thought the whole point of RTLIL is that it lets me avoid learning Verilog ;-)
<daveshah>
RTLIL is not intended to be human writeable outside of testing
<lukego>
(I started with some Verilog code that did ROM-like things as a "switch" statement but that didn't get mapped onto memory, just logic)
<daveshah>
You would want to use an initial block or $readmem[hb] to get $meminit cells
<lukego>
I'm hoping that RTLIL can serve as a foundation like FIRRTL i.e. provide "simple as possible but no simpler" abstractions to build on top of. Like an instruction set so to speak. Long term goal is not to write code by hand.
<lukego>
So I'm looking at ilang as the "main thing" here and the Verilog frontend as some esoterica.
<lukego>
but thanks I will chase these refs in the source :)
<daveshah>
The main reason not to hand write rtlil is a lack of parameterisation or generate-for type structuess
<daveshah>
Because it only exists after the first parts of elaboration are done
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<lukego>
Right. Maybe it's easiest to say that my goal is to write a frontend here, albeit I don't know much about how that will look yet, and so I'm trying to understand the "mid-end" for now
<daveshah>
I see
<lukego>
I'm thinking I'll start with RTLIL and add basic macro-like abstractions on top of that, and see how far that gets me as a learning exercise.
<lukego>
but I take the point not to expect a large corpus of hand-written RTLIL example programs
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<emily>
lukego: nmigen is an existing compiles-to-RTLIL eDSL
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<lukego>
Oh hey :-) Suppose that I wanted to get my hands on a high-end FPGA like a Kintex UltraScale+. How do hacker types usually do that? Seems like buying it off the shelf for list price is not the answer
<daveshah>
Have a look for used bitcoin miner boards?
<daveshah>
vcu1525
<daveshah>
and derivatives
<daveshah>
Or just use AWS F1 if you don't want to do any custom IO interfacing
<lukego>
I'm mostly intersted in I/O. My dream setup right now would be an AMD Threadripper with all of its PCIe lanes connected to FPGA(s)
<lukego>
So that's ~100 PCIe gen4
<daveshah>
Well if you only care about PCIe then AWS F1 might work
<daveshah>
But it's nowhere near that many lanes
<daveshah>
Something like x4 or x8 iirc
<lukego>
oh hm that's a really good point thanks!
<daveshah>
You can pay more for a box with something like 8 FPGA cards too
<lukego>
I'm really interested in networking applications where the FPGA would be hooked up to a bunch of 100GbE ports, but I think it's reasonable to treat that as a separate problem i.e. do the PCIe I/O and the Ethernet I/O work separately.
<lukego>
That sounds extremely promising. I'd like to do things like benchmark the CPU from the PCIe side to see where the pain ports are on the uncore/cache/ram
<lukego>
and an EC2 machine with 8xFPGA is probably a perfect solution for 0.1% the cost of buying the equipment for a 10 minute test.
<daveshah>
The one with 8 cards is $13/hr
<daveshah>
Even if you used it 24/7 it would be good value compared to buying in low qty
<daveshah>
Such is the discount that Amazon gets
<lukego>
So even cheaper because I don't think you get that hardware for $13K :)
<lukego>
Yeah I've been told privately that I would faint if I saw what Amazon pay for FPGAs.
<daveshah>
I would guess it is about 10-20x cheaper than DigiKey list
<lukego>
Seems like an anti-hacker conspiracy when BigCo and universities all get 10x discount but oh well
<lukego>
I suppose that if you found the right approach to Xilinx etc they would shower you with hardware e.g. if you are consulting on a project for one of their big customers/prospects.
<lukego>
but it's exhausting to play that game :)
<daveshah>
Even iCE40s have at least a 5x discount in 1e6 quantity
<daveshah>
I've been there before and it's easier said than done
<lukego>
Quantity sure makes a difference. I wanted to buy an ECP5 based NIC but it costs like $600 and that just seems like a lot compared with the FPGA, even though I know that's the reality of producing the boards for a really low quantity market.
<daveshah>
The first quotation I saw as a small company in the UK a few years ago for 1k Zynqs was above DigiKey single pricing
<daveshah>
For the smaller parts it seems like 100k is where it gets good
<lukego>
thanks muchly for the tips
<lukego>
lunch time here
<daveshah>
Enjoy
<lukego>
So follow-up question if I may :-) Supposing I would ultimately aim for EC2 as a high-end FPGA env. How might I prototype in a meaningful way e.g. with affordable hardware that I can use as a proxy for the real thing? And could I use Yosys/nextpnr for F1 or is that a different universe?
<mwk>
yosys, yes; nextpnr, no
<sorear>
you'll likely have a rather small number of pins you can connect to pcie lanes per fpga
<mwk>
that too
<mwk>
unless you get one of the outrageously expensive ones
<sorear>
I haven't run the numbers for ultrascale+ but on ecp5-5G the aggregate throughput of the "slow" I/Os is about 6x the aggregate throughput of the fast IOs/SERDESes because there are so many more of the former
<daveshah>
well nextpnr and rapidwright is a possibility for ec2
<daveshah>
Given it needs a dcp rather than a bitstream anyway
<daveshah>
But the router can't handle such big designs on a Xilinx arch at the moment
<daveshah>
Some hacking of pblocks would also be needed to integrate with the fixed ec2 logic
<lukego>
Seems like F1 instance FPGAs have PCIe gen3 x16 each. That would be 1Tbps of total PCIe bandwidth on a server with 8x FPGAs. Guessing that's NUMA so 0.5Tbps per node. Respectable. Even better if PCIe gen4 comes and doubles that.
<lukego>
Hopefully you get full control of the pins attached to PCIe? e.g. to run some small custom PCIe DMA load generator.
<daveshah>
I'm not sure, I know there is some logic that they provide
<sorear>
no
<lukego>
I suppose that being familiar with Amazon F1 doesn't hurt in itself because whoever uses that in production probably has deep pockets.
<sorear>
there's a "shell" which includes all of the pcie bits, you get an AXI4 interface
<lukego>
gack
<lukego>
well, maybe fine, do you think it limits performance?
<sorear>
I haven't actually tried but I doubt it's a bottleneck for streaming workloads
<lukego>
I'm in the packet networking domain so I'd be using the FPGAs as a proxy for NICs. Like, how much network traffic can an application keep up with, including all the messy bottlenecks like PCIe/RAM/NUMA. But also interested in seeing what can be done directly on the FPGAs.
<sorear>
"full control of the pins attached to pcie" sounds like it would have fun security implications for f1.2xlarge
<daveshah>
Yeah
<lukego>
Maybe it's a blessing to have a simplified interface really. Just provided it's not de-optimized for the specific intended purpose. always a risk when benchmarking and looking for fundamental limits.
<lukego>
I suppose that for dev purposes you would want a board with an equivalent PCIe-AXI4 bridge? Is that something straightforward?
<daveshah>
The Xilinx Alveo U200/U250 are probably the closest to that
<lukego>
not so easy on ECP5?
<daveshah>
afaik noone has done full open PCIe on ECP5
<lukego>
Maybe it's worth being in the Xilinx universe when developing for F1 anyway
<daveshah>
I suspect you will hit timing and utilisation limits on ECP5 quickly
<daveshah>
for what you are doing
<lukego>
Seems like ~$5K for those cards. Alternative might be to just develop against a dummy host / AXI4 stub?
<lukego>
But... quite a lot of ground to cover before this becomes relevant. I have soldered a CAT5 cable onto my TinyFPGA BX and I don't plan to buy any more hardware until I've successfully spammed out 10BaseT ethernet packets from that. Just stubbornly want to write the packet generator in RTLIL :)
<daveshah>
Sounds like fun
<lukego>
(And I must remember that my most ambitious FPGA designs to date have been variations on "blink this LED" and I'll now come facee to face with my own incompetence :-))
<lukego>
There's a neat dirty ethernet hack that I found here https://www.fpga4fun.com/10BASE-T0.html but I didn't like that their hard-coded packet seems to be synthesied as logic instead of ROM :)
<tpb>
Title: fpga4fun.com - 10BASE-T FPGA interface 0 - A recipe to send Ethernet traffic (at www.fpga4fun.com)
<ZipCPU>
10BaseT? Why not 100BaseT? Or GbE?
<lukego>
iCE40 with no SerDes
<lukego>
This is a gating example. I'll allow myself to buy an ECP5-Versa board with 1G after I make this work :)
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<ZipCPU>
100BaseT should still work ... RMII uses four wires ganged together at 25 Mhz. Shouldn't be much of a problem, and might be easier to find the hardware for.
<lukego>
I also think it's a bit cheeky to be doing ethernet using generic I/O pins and maybe it's easier to get away with that at lower speeds? There's no PHY so no RMII just wires soldered between the cable and the FPGA
<lukego>
(maybe I should have emphasised "dirty" over "neat" in my description ;-))
* ZipCPU
shudders at the thought of not using a PHY
<lukego>
well it only needs to send one packet and I'll be happy. I'll put a UDP envelope that can get it routed to the other side of the world and that will make it seem like an accomplishment :)
<ZipCPU>
Only if you can verify that the task was accomplished
<ZipCPU>
ICMP is often easier for that purpose
<ZipCPU>
Don't forget, though, that you can't do that without also supporting ARP .... :O
<lukego>
I'm prepared to be dirty on this level :-) I'll skip ARP by hardcoding the DMAC and I'll receive the packet using tcpdump so it doesn't matter if the receiver lkes it or not :)
<lukego>
I have almost no experience with FPGAs but I have spent most of my adult life doing inadvisable things with IP networks :)
<lukego>
btw love your blog! once I have my feet wet I am planning to go carefully through your intro to formal posts
<ZipCPU>
Awesome!
<lukego>
actually thanks for the RMII suggestion btw! maybe the next baby-step project for me would be to buy a 100M PHY and hook that up to my breadboard. That could be an intermediate step between this 10M hack and the ECP5 1G board.
<lukego>
Maybe I could even scavenge a PHY from a derelict circuit board lying around here somewhere..
<lukego>
I have splurged on a new soldering iron that will arrive next week so I'm itching for such a project. I decided that I've gotten my money out of the ~$5 aliexpress one now.
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<emily>
lukego: btw, I used to read your blog a bunch many years ago, so belated thanks from a fan of obscure languages and environments :)
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