clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<ZirconiumX> https://github.com/YosysHQ/yosys/issues/1531 <-- While this is probably a Yosys bug, this feels like enough of a corner case that it could equally be Verilog.
<tpb> Title: Assignment of 0 to for loop variable leads to a 1 in MSB · Issue #1531 · YosysHQ/yosys · GitHub (at github.com)
<ZirconiumX> Or maybe my Verilog knowledge just sucks
<mwk> hmm
<mwk> FWIW i[1:1] evaluates to 1'bx here (in yosys), not 1'b1
<mwk> okay, so the AST looks reasonable before simplification and already has 1'bx after simplification
<mwk> simplify.cc, 3769 LOC
<mwk> am I brave enough...
<mwk> oh heh
<mwk> okay, I think I see the bug
<mwk> line 1191: I'm reasonably sure we should be converting the value to the target register's width
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