clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<emeb_mac> it's been a few months since I last tried to build yosys. just pulled from git and tried to build and got this clang crash: https://pastebin.com/0bfU2aEi
<emeb_mac> Note - this is on an RPi4 w/ latest raspbian
<emeb_mac> yosys previously built fine on this HW, but with earlier raspbian.
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<turq> I'm new to fpga, and I have a question about how to go about debugging a problem
<tpb> Title: 1q.md · GitHub (at gist.github.com)
<turq> if anyone is able to give some feedback, I would very much appreciate it since I'm sort of stuck :)
<daveshah> First of all, I would create a design that just uses an `assign` to connect rx to tx
<daveshah> That will loop characters around and test that the serial port is working
<daveshah> I would also check that baud rate etc is set correctly
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<turq> thank you daveshah. I have checked the baud rate, I'll try the assign statement
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