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<ZirconiumX>
So, `help memory_bram` talks about `enable X` which is the number of "enable bits". Are these clock enables? Byte enables? Read/Write enables?
<daveshah>
Latter two
<daveshah>
read/write enables
<daveshah>
`enable X` means X read/write enables for a port each enabling a "byte" of width W/X (W being the width of the port)
<daveshah>
as an example, a 32-bit port with 8-bit byte enables would have `enable 4 ...`
<ZirconiumX>
Right, okay
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<ZirconiumX>
If I do something like `input [31:0] A, B;`, how wide is B? 32 or 1?
<ZirconiumX>
Given this is Verilog, I figured I'd best ask before deciding
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<rvense>
or maybe they get sixteen bits each
<ZirconiumX>
God I hope not.
<rvense>
the nets "A", "," and "B" are each 10 2/3 bit
<rvense>
... i think the real answer is 32. i've used it like that, at least, in verilog that does what i expect.
<ZipCPU>
No, no, no ...
<ZipCPU>
input [31:0] A, B; would declare two 32-bit inputs, A and B
<ZipCPU>
If you use: `default_nettype none (highly recommended) then this should read: input wire [31:0] A, B;
<ZirconiumX>
I'm writing Yosys techmap passes, and mapping primitives is not a very fun process
<ZipCPU>
Enjoy ;)
* ZirconiumX
cries
<ZirconiumX>
Because of the lack of documentation on what I'm trying to do, I'm resorting to essentially compiler-driven development
<ZirconiumX>
Except that with error messages such as "WYSIWYG RAM primitive has too many bits", I've kinda hit a brick wall here.
<ZipCPU>
Sigh.
<ZipCPU>
One of those things I've never tried to do is to write my own techmap passes
<ZirconiumX>
I mean, techmap *is* a useful thing.
<ZipCPU>
Others here on the channel have. Hopefully they'll be able to pipe up with a word (or two) of encouragement
<ZipCPU>
What sort of items are you trying to map?
<ZirconiumX>
Ironically, Quartus itself doesn't instantiate primitive RAM blocks directly but instead instantiates a megafunction to lower to the correct primitive
<ZipCPU>
Cyclone-V?
<ZirconiumX>
ZipCPU: ^
<ZirconiumX>
Yep
<ZipCPU>
Yeah, I've done some work with Quartus tools myself
<ZipCPU>
Just not with my Cyclone_V and Yosys (yet)
<ZipCPU>
Does Yosys support defparam? I didn't think so ...
<ZirconiumX>
You're looking at basically the lone person for Yosys-on-Cyclone-V
<ZirconiumX>
write_verilog -defparam
<ZipCPU>
Ah, okay
<ZirconiumX>
I think Quartus supports new-style parameter definitions #(...) but since synth_intel uses this, I'm following them
<ZipCPU>
So ... is yosys doing the techmap only to have Quartus choke? Or is Yosys itself choking on the techmap?
<ZirconiumX>
Quartus is the one choking on this
<ZirconiumX>
I'm writing a techmap pass to produce this code
<ZipCPU>
Is this the "right" code for what you are trying to create?
<ZirconiumX>
Except I'm having issues with the Quartus primitives
<ZirconiumX>
I have no idea what the "right" code is, because Quartus primitives have no public documentation
<ZipCPU>
Why not instantiate the same underlying design in Quartus and see what it does with it?
<ZirconiumX>
synth_intel uses an altsyncram megafunction for this, but I have a distaste for the Altera IP library
* ZipCPU
shares ZirconiumX's distaste
<ZirconiumX>
I helped 'quark with adding Quartus support to nMigen
<ZirconiumX>
The IP library is horrendously inconsistent
<ZipCPU>
Yosys hasn't done the CV before, tho, right?
<ZipCPU>
(CV = Cyclone-V)
<ZirconiumX>
It does, kinda, but the previous "maintainer" - dh73 - used a Cyclone IVe, and the two families are fairly different
<ZirconiumX>
So I have a custom script flow for Cyclone V, which includes things like LUTRAM and BRAM mapping
<ZirconiumX>
synth_intel has no LUTRAM mapping, and I had to disable BRAM mapping for CV because it tries to instantiate a CIV BRAM cell on a CV
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