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<bwidawsk>
has anyone looked into using yosys for opencl synthesis, or something equivalent to Altera's opencl sdk?
<daveshah>
I imagine what you'd want would be higher level than Yosys?
<bwidawsk>
Most likely, although it might be feasible for a subset of opencl to have a frontend parser for it... maybe
<daveshah>
I expect it would be easier to have a separate tool that generates RTLIL or Verilog
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<Kokjo>
Hey! anyone here have datasheets for the voltage regulators used on the icebreaker board? I wish to know if i can run the icebreaker of 2 3V cr2032 coincells.