clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<bwidawsk> has anyone looked into using yosys for opencl synthesis, or something equivalent to Altera's opencl sdk?
<daveshah> I imagine what you'd want would be higher level than Yosys?
<bwidawsk> Most likely, although it might be feasible for a subset of opencl to have a frontend parser for it... maybe
<daveshah> I expect it would be easier to have a separate tool that generates RTLIL or Verilog
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<Kokjo> Hey! anyone here have datasheets for the voltage regulators used on the icebreaker board? I wish to know if i can run the icebreaker of 2 3V cr2032 coincells.
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<esden> Kokjo: both regulators (3v3 & 1v2) are SPX3819. https://www.maxlinear.com/ds/spx3819.pdf
<esden> errm sorry ... these are the Exar parts that I used: https://datasheet.lcsc.com/szlcsc/Exar-SPX3819M5-L-3-3-TR_C9055.pdf
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<Kokjo> esden: cool! It seems possible, thanks!
<esden> Kokjo: good luck! :D
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