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<pepijndevos>
Will yosys glue together brams to make bigger ones?
<tnt>
yes
<pepijndevos>
sweet
<daveshah>
It will also duplicate BRAMs in other cases, like if there is more than read port
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<ZirconiumX>
It seems to have issues if you want multiple write ports though
<tnt>
Well, it can't invent logic that doesn't exist :p
<tnt>
Like how do you implement two write ports if the underlying logic only supports one ?
<ZirconiumX>
tnt: There are papers on this very subject
<ZirconiumX>
For N write ports, you make N duplicates of the memory, and then synthesise a small look-up table for which write port has the most recent version of the input
<ZirconiumX>
The resulting table is much smaller than creating a multiport RAM out of DFFs
<daveshah>
There's also a trick with XORs
<daveshah>
I'm not sure any of these tricks work for multiple write ports in different clock domains
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