clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<ZirconiumX> daveshah: So, I've been trying to bugpoint a FlowMap crash, but while the original Verilog source works, exporting it to RTLIL and re-importing produces a "Module `model_fifo' is used with parameters but is not parametric!" error
<ZirconiumX> Well, "works" as in "causes a FlowMap crash"
<daveshah> What commands are you using?
<ZirconiumX> To dump RTLIL? Just `write_ilang`
<ZirconiumX> (with a filename)
<daveshah> What are you doing to it before writing? Might be worth trying a prep -flatten before writing
<daveshah> Or at least hierarchy -top before writing if you don't want flattened rtlil
<ZirconiumX> Yeah, hierarchy -top prunes the erroring module, which is good enough
<ZirconiumX> Since being able to prune modules means bugpoint converges faster, it should be a bit easier to work with?
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<rjo> hello! on ice40, is anyone using DYNAMICDELAY in the SB_PLL40_*? any code? any reports that it works? does changing DYNAMICDELAY require a RESETB pulse + wait for lock?
<rjo> i have been playing with it for a while and can't seem to make any difference.
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<ZipCPU> rjo: Hello! Welcome to the channel!
<ZipCPU> Although ... I'll admit, I haven't tried the DYNAMICDELAY on an iCE40 at all
<ZipCPU> I'm also wondering currently if the similar primitive for the ECP5 does much ... but that's another story
<rjo> Well. It doesn't do anything on ice40 because the parameter is ignored by nextpnr...
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