clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<somlo> daveshah: tried merging xc7dsp on top of yosys master, getting some conflicts I'm not sure I know enough to resolve...
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<pepijndevos> ZirconiumX, did you ever figure out what the difference is between the always block and the assign?
<pepijndevos> I just write (bad) verilog by copying what I see
<ZirconiumX> pepijndevos: "assign" is terser here, and if your RHS expression is a constant then "always @(*)" will never evaluate.
<ZirconiumX> But in this case they are equivalent.
<ZirconiumX> "always @(*) A = B" is equivalent to "assign A = B" if A is a register and B is not a constant
<ZirconiumX> I asked Her Quarkiness about it.
<ZirconiumX> pepijndevos: I feel like you should use wires more often, especially when you're doing things like copying DUT values.
<ZirconiumX> For that you need to use "assign"
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<pepijndevos> ZirconiumX, could very well be
<pepijndevos> As opposed to registers?
<ZirconiumX> Yeah
<ZirconiumX> Though it shouldn't make too much difference for simulation
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<somlo> daveshah: also, do you know if xc7dsp is a candidate for inclusion into the upcoming 0.9 release?
<daveshah> somlo: I'll have a look at the conflicts on tuesday
<daveshah> No, xc7dsp will be 1.0/0.10/10/whatever
<daveshah> 0.9 is pretty much frozen now
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<somlo> daveshah: ok, thanks!
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