clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<pepijndevos> Is $readmemh synthesizable to some block ram primitive?
<daveshah> Yes, it becomes a $meminit in Yosys, which then becomes an initialised bram
<pepijndevos> awesome
<pepijndevos> I'm used to making a bram in quartus, so I'm a bit unsure what kind of code I have to write to make a bram in yosys. I hope if I just make a huge array it'll just magically work :)
<ZipCPU> Pretty much, but there are some "rules" you need to follow to be successful
<ZipCPU> Basically, you can't ask for an array that the hardware cannot support
<pepijndevos> hmmmm
<pepijndevos> I guess I'll just mess around until I get a $meminit, or are the some examles/libraries somewhere?
<pepijndevos> "ZipCPU: there is a tutorial for that" ;)
<pepijndevos> Thanks
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<bwidawsk> this isn't actually me, right? https://travis-ci.org/YosysHQ/yosys/jobs/567999486
<tpb> Title: Travis CI - Test and Deploy Your Code with Confidence (at travis-ci.org)
<daveshah> No, looks like travis having a sad moment
<daveshah> I'm not sure if it's actually possible to force a rebuild (I'm logged in as a repo admin) without force-pushing :/
<bwidawsk> yeah - I don't see anything
<bwidawsk> I can force push... I had a grammar error in my commit msg anyhow
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<bwidawsk> is the ANSI C style module declarations frowned upon for new files, or generally?
<ZipCPU> bwidawsk: Depends upon who you ask
<ZipCPU> Some folks swear by it
<bwidawsk> It's my preference, but I'm a long time C coder and new to verilog, so I might be the minority
<ZipCPU> Nah, I don't think the lines are so clearly delimited
<ZipCPU> I don't use the ANSI style, but it seems like I'm forever evaluating code that does
<ZipCPU> Sometimes I even slip into using it
<ZipCPU> I'm not sure I could give you a reason not to use the one or the other. Pick the one you like.
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<bwidawsk> ZipCPU› thanks
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