clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<promach> What does "loop warning" means for "ltp -noff" ? Can I just ignore the loop warning ?
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<janrinze> a bit curious here.. the ecp5 evaluation board runs the design well after uploading with the openocd tools through make.
<janrinze> But after powercycle the design has reverted to the default design of lattice.
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<ZirconiumX> janrinze: FPGAs are volatile devices
<ZirconiumX> It's possible it didn't get written to the flash or whatever
<janrinze> that's the point here. normallly the tools ensure a wrtite to flash
<janrinze> oops .. 'write'
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<daveshah> There are a few scripts lurking for programming ECP5 SPI flash rather than SRAM over JTAG
<daveshah> I don't have links to any off hand though
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<tnt> daveshah: is that using bscan or uploading a bitstream to the fpga that allows it to bridge jtag to spi flash ?
<daveshah> There is some kind of built in SPI over JTAG "tunnelling"
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<janrinze> daveshah: I've been looking around but all the makefiles look the same with the same svf scripts
<cr1901_modern> daveshah: While it's on my mind, when andresnavarro RE'd the compression code, were you ever able to test it on ECP5 family?
<daveshah> janrinze: I don't think any of the prjtrellis examples use it. I think it was done by Greg: https://gist.github.com/gregdavill/4f9f536757966171ef974f98348bbacb
<tpb> Title: background_spi_test.py · GitHub (at gist.github.com)
<daveshah> cr1901_modern: no, I don't think I ever did
<cr1901_modern> Just wondering is all :P
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<janrinze> daveshah: Greg seems to have several nice ecp5 projects on github. Mostly kicad and strangely the python script i could not find in github, only on the gist
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