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<pepijndevos>
Can Yosys (not nextpnr) give me my critical path?
<pepijndevos>
Or alternatively, how hard would it be to use the generic target for 74xx?
<tnt>
yosys has no timing analysis or timing data
<pepijndevos>
Not even a simple unit delay something to synthesize for speed?
<tnt>
not that I know
<tnt>
it's not timing driven synthesis at all.
<daveshah>
ABC uses this stuff internally
<pepijndevos>
Ah I see
<daveshah>
ABC does do timing driven synthesis, using delay info from liberty files (for ASIC), unit delays (for `abc` LUT synthesis) or box/lut files (for `abc9` LUT synthesis)
<tnt>
daveshah: really ? It optimize for depth ?
<daveshah>
Yes
<daveshah>
However, `abc` doesn't count boxes (e.g. carries) in depth - but `abc9` does
<pepijndevos>
(what's the diff between abc9 and abc?)
<daveshah>
abc9 uses newer commands in abc that are capable of handling whiteboxes
<pepijndevos>
But abc9 only does LUT, right?
<daveshah>
and uses a different format (xaig rather than blif) to better represent these whiteboxes
<daveshah>
Yes, right now anyway
<pepijndevos>
So can I extract this timing stuff from abc, or would it be easier to somehow use the generic nextpnr?
<daveshah>
You probably won't get much of use from abc
<pepijndevos>
Right now 74xx liberty has no real timing info, but I want to get a rough idea of the maximum frequency of my 74xx CPU :)
<daveshah>
tbh topological timing analysis is sufficiently simple I'd just hack something together than trying to do it in nextpnr
<pepijndevos>
Right... just export to json and hack up some python
<daveshah>
just toposort all your combinational cells and walk forward determining max delay
<tpb>
Title: Topological sorting - Wikipedia (at en.wikipedia.org)
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<daveshah>
Incidentally, the long term (end of the year at the earliest) plan is to represent timing information inside Yosys using `specify`blocks in the Verilog cell white/blackbox libraries
<ZipCPU>
davehah: Really? Wow. I like it, but I am a bit surprised by the decision
<ZipCPU>
pepijndevos: If you are interested in critical path timing information from Yosys today, consider the LTP command. It's not quite what you want, but it is related
<ZipCPU>
LTP = Longest topological path
<pepijndevos>
oh!!
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<ZipCPU>
Don't forget to exclude FF's, since they aren't typically part of any actual timing chain
<pepijndevos>
Will -noff still work after techmapping?
<ZipCPU>
Not likely, but there are ways to still get it to work
<ZipCPU>
(If I remember them)
<ZipCPU>
Let's see ... it was something like "ltp t:*FF* %n" IIRC, where you can replace *FF* with whatever you are using for FFs
<pepijndevos>
That seems to work! But... the signal names are all like $abc$1375$auto$ghdl.cc:290:import_module$47[15] so a bit hard to tell what it means
<ZipCPU>
Yeah, exactly
<ZipCPU>
So ...
<ZipCPU>
I talked with clifford about this, and got him to name both inputs and outputs of a FF with the name of the FF (usually found w/in the design)
<ZipCPU>
Check for the first and last element in the LTP string, and that should help
<ZipCPU>
You can also use "show" to figure out what's going on, perhaps even increasing the size of the incoming cone with something like "%ci1" or some such
<pepijndevos>
The string I pasted was the last one... the first one is just a human-named signal
<pepijndevos>
Show is not a bad idea
<pepijndevos>
What's that bit about the incomming cone?
<ZipCPU>
The incoming cone shows all the logic incoming to the currently seleected set of elements. IIRC, %ci1 shows adds all the inputs to the current selection to the selection, %ci2 adds the inputs to those inputs and so on
<ZipCPU>
There's also an outgoing cone that might be useful, %co with the numbers having the same meaning. So you might consider adding %co1 to your LTP and see what happens
<pepijndevos>
oh, I can pass that to show you mean. Good idea... running show on the whole design.. takes a while.
<ZipCPU>
That should help if the result was just before a FF and the name was still incomprehensible
<pepijndevos>
Yay, %c02 actually shows the flip flop it goes to
<pepijndevos>
Can I somehow feed the output of ltp as the selection to show?
<ZipCPU>
Yes
<ZipCPU>
... although I can't remember how to do it right now ... :/
<pepijndevos>
lol
<pepijndevos>
Going over the help file it's not immediately obvious to me either. Maybe something with the select command?
<pepijndevos>
Looking at the source code I also don't see an obvious way to do it.
<pepijndevos>
Except of course parse the output of the command and then convert it to a selection with a hacky Python script.
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<tnt>
pepijndevos: how many chips is that cpu ?
<pepijndevos>
82 last time I checked
<tnt>
Oh, that's reasonable.
<pepijndevos>
Hrmmmmmm right now the longest part of the critical path is the logic from the alu output to the register depending on the state and the opcode.
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<pepijndevos>
omg, according to my rough estimate my cpu should be able to run at 10MHz. All 74AC chips seem to have a worst case delay of 10ns, so with a critical path of 9 and a worst case set-up time of 5ns...
<pepijndevos>
Of course in my bit serial archt that's only 0.5MHz instructions per second...
<pepijndevos>
Typical propagation delays are more like 5ns, so 20MHz is not impossible... maybe
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<pepijndevos>
How well are source attributs preserved through synthesis? You could make a script that reports how many gates a line of code produced
<daveshah>
Not very well - ABC's architecture means that input code and gates produced don't correlate in any meaningful way
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<ZirconiumX>
Can somebody clarify the difference between $lcu and $alu? My understanding is that $alu is an adder/subtractor and a $lcu is a fast(ish) carry chain, but the line gets blurry when you need a carry chain for long additions
<daveshah>
`$alu` is usually the important one to map for FPGA things
<bwidawsk>
is yosys smart enough to use carry chains in FPGAs for connected arithmetic units?
<daveshah>
What do you mean for "connected arithmetic units"?
<daveshah>
btw, ZirconiumX, I just checked and nothing in Yosys should create a `$lcu` - but techmap will downmap a `$alu` to one
<bwidawsk>
output of adders in ALMs (or whatever the generic term for that is)
<daveshah>
Yes, stuff like + and - will become carry chains
<daveshah>
although this is more a function of the architecture techmap rules than Yosys itself
<bwidawsk>
well the attempt to use adjacent ALMs
<bwidawsk>
I suppose that is part of PNR
<ZirconiumX>
Should be PnR
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