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<ZirconiumX>
Huh, this is interesting: the Cyclone 10 GX ALM strongly resembles the Cyclone V ALM, and the Cyclone 10 LP ALM strongly resembles the Cyclone IV ALM
<ZirconiumX>
This is useful information
<daveshah>
Cyclone 10 is just a rebranded Cyclone IV
<daveshah>
which is just a die shrink of the Cyclone III
<daveshah>
Not even sure if the JTAG IDs changed
<ZirconiumX>
The LP seems like it
<ZirconiumX>
But the ALM is different between the GX and LP
<daveshah>
Ah yes, meant LP
<daveshah>
GX may well just be a V though
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<ZirconiumX>
It does appear to be a V
<daveshah>
Intel are too lazy to update the JTAG IDs so it's usually pretty obvious
<daveshah>
From memory of playing with the Cyclone III, the Quartus programmer actually asks you which device you have
<daveshah>
Most other companies (Lattice certainly) put the IDCODE in efuse/otp so they can do binning after production testing
<ZirconiumX>
So, it seems the Intel range is architecturally split into IV/10LP/MAX10 and V/10GX
<ZirconiumX>
Which is useful from a coding standpoint
<ZirconiumX>
Since Project Chibi documents the MAX10 (not very well >.>), that information should translate to the other two
<daveshah>
Yup
<daveshah>
There will doubtless be some equivalences to Stratix/Arrias too
<daveshah>
No FPGA company has *that* many different arches...
<daveshah>
Chibi documents the MAX V iirc
<ZirconiumX>
Ah, yes
<ZirconiumX>
The MAX V seems to be related to the IV LE
<ZirconiumX>
But the flop is more advanced, it appears
<ZirconiumX>
The MAX V LE appears to be from a Cyclone I?
<daveshah>
Yes, I think rqou mentioned something like that at the time
<ZirconiumX>
This handbook refers to it as just "Cyclone", so yeah
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