clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<pepijndevos> How does the extract pass work with parameters?
<pepijndevos> -ignore_parameters Do not use parameters when matching cells.
<pepijndevos> So what does it do to "use parameters"?
<pepijndevos> It seems extract is also extremely picky about using for example 1 or 8'b1
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<pepijndevos> Does a techmap "inherit" the parameters of the thing it replaces?
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<pepijndevos> Are there any magic rules for when a techmap matches or not? Mine does not, for some reason.
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<pepijndevos> ERROR: (ASSERT MODE) No matching template cell for type \$counter16 found.
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<ZirconiumX> [16:07:31] pepijndevos: Does a techmap "inherit" the parameters of the thing it replaces?
<ZirconiumX> If you use a _TECHMAP_REPLACE_ I think so
<ZirconiumX> [16:48:29] pepijndevos: Are there any magic rules for when a techmap matches or not? Mine does not, for some reason.
<ZirconiumX> Either the module is named the same as the cell you're trying to replace, or you have (* techmap_replace = "target_cell" *) above it, and _TECHMAP_FAIL_ is zero
<ZirconiumX> That's when it matches
<pepijndevos> ZirconiumX, it's the dollar signs... If I'm trying to act cool and put dollar signs in my counter like a real techmap it fails
<pepijndevos> If I just extract and techmap without the dollars it breaks. I think I'm not escaping stuff enough/too much
<ZirconiumX> The documentation says techmap -assert errors out if a cell name doesn't end with an underscore
<ZirconiumX> If you called your cell $counter16, that'll error because it does not end with an underscore
<pepijndevos> https://github.com/YosysHQ/yosys/blob/master/passes/techmap/techmap.cc#L413 i think it means it'll ignore anything with an underscore if I read the code correctly
<tpb> Title: yosys/techmap.cc at master · YosysHQ/yosys · GitHub (at github.com)
<ZirconiumX> Correct
<ZirconiumX> Conversely since your cell does not end in an underscore, it's an error
<pepijndevos> Yea, but if I just put an underscore it'll not error and still not replace, I think it's purely that it never asserts on underscored things.
<pepijndevos> So if I call my extracted cell counter16 and the techmap on counter16 all is good, but if I call my extraction $counter16 or \$counter16 or whatever, nothing works.
<pepijndevos> Or even $_COUNTER16_ or anything else that I've tried.
<pepijndevos> So I'm not understanding anything about the naming convention and escaping. Like, I've seen \$thing and \\$thing and $thing in various places
<pepijndevos> I guess I don't really care about the dollar thing, except counter8 seems so common it might come up in normal code, so I thought I'd stick with what seems to be a convention for dollar signs for cells.
<pepijndevos> Should I just call it 74xx_counter and be done with it?
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<pepijndevos> Cool, techmap kinda works, simulation super broken.
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<pepijndevos> it's working! Kinda??
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<ZirconiumX> pepijndevos: so when are you shipping a PicoSoC to me?
<ZirconiumX> :^)
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<pepijndevos> ZirconiumX, hopefully near the end of the holiday :^)
<ZirconiumX> I think the multiplier would be painful
<pepijndevos> The pwmled is now 7 chips
<ZirconiumX> Because of counter recognition?
<pepijndevos> Yes
<pepijndevos> But it's extremely picky, so you pretty much have to want to use it.
<pepijndevos> Originally I wanted to use an up/down counter, but it seems 74161 is pretty much the only thing that's still on sale.
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<ZirconiumX> I don't think you can meaningfully reduce that benchmark any further
<pepijndevos> With an up/down counter you could make a sweeeet stack pointer, but at least maybe this is somewhat useful as an instruction pointer.
<pepijndevos> There is a sexy sexy 8-bit up/down counter IC, but I don't think it's sold anywhere.
<ZirconiumX> Which model?
<pepijndevos> 74x867
<ZirconiumX> pepijndevos: have you seen the 74x4040?
<pepijndevos> eh, yea... can't remember the details
<pepijndevos> 12 bits is a bit... odd, no preset, no up/down. So it could be a lot more efficient in some cases, and less useful in others.
<pepijndevos> Right now I have to specifically extract counter8, counter16 etc. and counter12 seems... not very common.
<ZirconiumX> Mmm
<pepijndevos> So for example, if I want to use it as an instruction counter, I need preset for jumps
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<pepijndevos> Although I'm not even convinced what I'm doing now will work for that...
<pepijndevos> Well, lemme push and you can have a look at it.
<GenTooMan> the 74hc191 still is produced?
<ZirconiumX> True, and Farnell sell it
<ZirconiumX> GenTooMan: though we prefer DIP over SOIC for this
<GenTooMan> ZirconiumX Nexperia and TI still make the DIP version as far as I know.
<sorear> kinda surprised you’re not just using quad nands etc
<ZirconiumX> TI are the one who sell DIPs for Farnell, and it's on back-order
<ZirconiumX> sorear: We're crazy not stupid
<GenTooMan> at least you are not making it with transistors.
<pepijndevos> 74x191 is actually a nice one maybe? Not really in AC or DIP but... it counts down.
<GenTooMan> the reason I bothered pointing it out.
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<pepijndevos> change.org petition: TI makes the whole 74xx series
<pepijndevos> sorear, part of me wants to do NOR and recreate the Apollo Guidance Computer
<daveshah> Why need a change.org petition when you have MPWs?
<pepijndevos> daveshah, what's MPW?
<daveshah> Multi project wafer
<daveshah> Relatively cheap way of making custom silicon
<pepijndevos> Are you suggesting I make an ASIC instead (boring), or produce my own 74xx chips (omg)?
<pepijndevos> Any idea what it costs to do that kind of stuff?
<daveshah> Latter
<daveshah> Probably a few thousand euros minimum
<pepijndevos> Okay, scrap the change.org, on to kickstarter hehe
<GenTooMan> then your biggest issue would become buffering and someone to package the chips. a single 8 inch wafer can get you quite a few parts I suspect.
<daveshah> Europractice 700nm, probably fine for any 7400, 300€/mm2, 5mm2 min
<daveshah> For 30 samples, excluding packaging
<ZirconiumX> That's a bit pricey, but would be funny
<ZirconiumX> On the other hand, why not just fabricate a PicoSoC directly?
<pepijndevos> That's what these Raven people did, no?
<pepijndevos> Or why not both?
<daveshah> That's already been done
<daveshah> Indeed
<ZirconiumX> pepijndevos: I'm going to disappoint you greatly
<ZirconiumX> "In my experience writing counter + 1 and counter + 1'b1 already causes a mismatch"
<ZirconiumX> Because 1'b1 is 1-bit, and 1 is 32-bit
<pepijndevos> I know, but yosys optimizes the useless bits away
<ZirconiumX> Sure, but they're semantically different and the compiler obviously has to keep semantics
<pepijndevos> I guess...
<daveshah> opt and wreduce should deal with the difference though
<pepijndevos> It just makes the counter extraction not very flexible.
<ZirconiumX> I'm reasonably sure Yosys turns, say, 4'b1 (i.e. 4'b0001) to 4'bxxx1
<ZirconiumX> But don't quote me on that
<daveshah> Unlikely
<pepijndevos> daveshah, if I put my extract pass *after* wreduce it doesn't match.
<daveshah> What does the netlist look like after wreduce (`dump` and `show` are helpful)?
<daveshah> You might want to use a wreduce'd counter (e.g. saved as il) as the needle in this case
<pepijndevos> That might be a good one...
<daveshah> After wreduce and clean, this produces three identical adders (A_WIDTH 4, B_WIDTH 1, Y_WIDTH 4, B connected to 1'b1)
<tpb> Title: Snippet | IRCCloud (at www.irccloud.com)
<pepijndevos> does opt do clean or are these different things?
<daveshah> opt does clean too (I didn't use opt for this test as it would actually merge all three adders)
<pepijndevos> yay that works
<pepijndevos> Now I wonder if it gets used in *any* of the other benchmarks...
<pepijndevos> The answer is no
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<matt`> hello! i'm having some trouble understanding a yosys error message: "found error in internal cell" where it's complaining about cell $_DFF_PP1. I'm experiencing this when running `synth_xilinx`; `read_verilog` works fine (although I do get a warning about tri-state logic from the same file triggering the error message). Is there a possibility this error means I'm using a tristate representation not supported by yosys? What does that
<matt`> error mean generally? That yosys isn't able to map the RTL to the available Xilinx cells?
<matt`> i'm running the current git master version btw
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<daveshah> matt`: I don't think this would be related to a tristate issue
<daveshah> A "found error in internal cell" is a Yosys bug
<daveshah> If your design isn't confidential, creating a Yosys issue would be helpful
<matt`> daveshah: i'll try to get this down to a minimal example and raise the issue. Thanks for the help! By the way, what does it mean that tri-state has limited support? is there somewhere in the documentation that says what is and isn't supported in that regard?
<daveshah> If it helps pinpoint the issue, a `$_DFF_PP1_` is the Yosys internal type for a single-bit D flipflop with an asynchronous set and rising edge clock
<daveshah> In practice I don't think it's so much that only a subset of tristate functionality is supported, as that tristate has a lot of different possibilities and not everything has been tested
<daveshah> This is particularly the case for the Xilinx flow which isn't so well used for designs with this kind of stuff
<matt`> gotcha. thanks again
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