clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
<sorear> right, it’s not emulating a latch, it literally is one
<sorear> it is synthesizing a latch from smaller components that are not themselves latches
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<cr1901_modern> What does a latch from smaller components look like then (note that yosys has a $dlatch cell, so it wouldn't go the "back to back NAND gates" route)?
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<sorear> I’d say a LUT programmed as a 2:1 mux, with the output fed back as one input
<cr1901_modern> That seems reasonable to me too. I'm doing a few experiments where I modify an ilang input (that was created from a "real" Verilog latch) and see what cells yosys infers
<cr1901_modern> One of them was a mux w/ feedback
<cr1901_modern> I think
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<maikmerten> hmmm... did something significant change within the last two weeks regarding yosys and nextpnr for the iCE40? My SoC went from ~2500 to ~3000 LCs, but f_max increased from ~35 MHz to ~40 MHz
<maikmerten> so that's quite something
<tnt> -relut was enabled by default yesterday.
<tnt> but ... I wouldn't expect that from it.
<maikmerten> ah, interesting
<maikmerten> is there a description on what it does?
<maikmerten> I'm invoking synthesis with "yosys -p 'synth_ice40; attrmvcp; write_json ./boards/hx8k-breakout/top.json'"
<maikmerten> is there a simple way to disable relut for testing?
<tnt> not really. I think the easiest is just to look at all the passes of synth_ice40 and call them manually and skip the unlut.
<maikmerten> ewww. ;-)
<maikmerten> I mean, the f_max is great, but I figure a noticable LC-increase was not anticipated?
<tpb> Title: synth_ice40: switch -relut to be always on by whitequark · Pull Request #1183 · YosysHQ/yosys · GitHub (at github.com)
<tnt> maikmerten: well, relut should yield a LUT decrease really ...
<maikmerten> yeah, it does say merging and stuff
<maikmerten> compiling https://github.com/YosysHQ/yosys/commit/a8c5f7f41ec0c829c29ae425b0074eb33fa2a30c (pre-enabling) to see if that makes a difference
<tpb> Title: synth_ice40: fix help text typo. NFC. · YosysHQ/yosys@a8c5f7f · GitHub (at github.com)
<maikmerten> yup, going back to that commit brings LC-count back to ~2500
<maikmerten> and f_max back to ~35 MHz
<tnt> maikmerten: and if you do synth_ice40 -relut with that version you see the LC increase ?
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<maikmerten> trying
<tpb> Title: debian Pastezone (at paste.debian.net)
<maikmerten> so relut *does* reduce the LC count
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<maikmerten> but nextpnr doesn't pack things as tightly anymore
<daveshah> Oh I think I know the problem
<daveshah> The LUT map ordering changed to accommodate abc9
<daveshah> This will cause the relut changes to no longer allow the LUT and carry to be packed together
<maikmerten> oh :-)
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<tnt> daveshah: what do you mean by lut map ordering ?
<daveshah> The $lut to SB_LUT port mapping
<tpb> Title: yosys/cells_map.v at master · YosysHQ/yosys · GitHub (at github.com)
<daveshah> abc9 maps such that LUT input 0 should be the fastest
<daveshah> But SB_LUT input 3 is the fastest
<daveshah> afk right now, so can't look in detail
<maikmerten> (is it useful if I provide my test case?)
<maikmerten> (as in the .json files with and without relut, the Verilog stuff is MIT licenced anyway)
<tnt> maikmerten: can you open an issue so this can get tracked ?
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<maikmerten> sure
<maikmerten> is this a nextpnr or yosys thing?
<tnt> Ah well, this might be https://github.com/YosysHQ/yosys/issues/1187 already
<tpb> Title: -relut appears to cause performance problems with ice40 synthesis · Issue #1187 · YosysHQ/yosys · GitHub (at github.com)
<maikmerten> I suspect former
<tnt> it's a yosys thing.
<maikmerten> okay, I see a similar LC ballooning thing there
<maikmerten> in my case, I at least get a wonderful f_max increase
<tnt> Most likely your critical path was not an adder. But in picorv32 I know the critical path has a carry chain in it.
<maikmerten> as far as I can tell my critical path is a subtraction, so there's a carry in there somewhere ;-)
<tpb> Title: debian Pastezone (at paste.debian.net)
<tnt> mmm, ok yeah, not all adders will be 'changed' by relut I guess.
<maikmerten> (yeah, 33 bit subtraction for "less than unsigned" cpu_inst.alu_inst.ltu)
<maikmerten> but the dramatic increase in f_max (veeeeeery nice) makes me wonder what it looked like before
<tpb> Title: diff --git a/techlibs/ice40/ice40_unlut.cc b/techlibs/ice40/ice40_unlut.cc index - Pastebin.com (at pastebin.com)
<tnt> maikmerten: can you give that a shot ?
<maikmerten> tnt, on yosys master?
<tnt> maikmerten: you can apply it on what you're using now and just check with -relut option.
<maikmerten> alright
<maikmerten> tnt, sorry for my stupidity, but is this something "git am" should apply or is this a "raw" diff?
<tnt> that's a raw diff
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<maikmerten> patching file techlibs/ice40/ice40_unlut.cc
<maikmerten> patch unexpectedly ends in middle of line
<maikmerten> patching file techlibs/ice40/synth_ice40.cc
<maikmerten> Hunk #1 FAILED at 344.
<maikmerten> 1 out of 1 hunk FAILED -- saving rejects to file techlibs/ice40/synth_ice40.cc.rej
<maikmerten> will manually replicate
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<tpb> Title: debian Pastezone (at paste.debian.net)
<maikmerten> that brings down LC usage compared to no relut
<maikmerten> too bad f_max is back to normal ;-)
<maikmerten> but one cannot have everything
<maikmerten> (the subtraction carry chain is the critical path again)
<tnt> maikmerten: did you try --placer heap ?
<maikmerten> tnt, yup, it's my default placer
<maikmerten> nextpnr-ice40 --randomize-seed --placer heap --hx8k --json top.json --pcf hx8k-breakout.pcf --asc top.asc --freq 28
<tnt> OTOH the fmax doesn't mean much because you ask for 12 MHz ... so it will stop even searching for anything better.
<maikmerten> oh, in the past I didn't really an effect on f_max when asking for a higher frequency
<maikmerten> but then again, I didn't try that in a while
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<maikmerten> yeah, asking for 40 MHz (which appears to be attainable with yosys master by accident) doesn't really move things
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<tnt> what soc is it btw ?
<tpb> Title: GitHub - maikmerten/spu32: Small Processing Unit 32: A compact RV32I CPU written in Verilog (at github.com)
<tpb> Title: badapple.mp4 - Google Drive (at drive.google.com)
<maikmerten> tnt, I'm using the HX8K breakout board, with some custom additions: https://drive.google.com/file/d/1-8XCHNu_fg2EPYMHQbVBrB6EDCN_Jlqu/view?usp=sharing
<tpb> Title: IMG_20190623_211623362.jpg - Google Drive (at drive.google.com)
<maikmerten> (I need to update that block diagram, the VGA unit is not text mode anymore)
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