<sorear>
right, it’s not emulating a latch, it literally is one
<sorear>
it is synthesizing a latch from smaller components that are not themselves latches
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<cr1901_modern>
What does a latch from smaller components look like then (note that yosys has a $dlatch cell, so it wouldn't go the "back to back NAND gates" route)?
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<sorear>
I’d say a LUT programmed as a 2:1 mux, with the output fed back as one input
<cr1901_modern>
That seems reasonable to me too. I'm doing a few experiments where I modify an ilang input (that was created from a "real" Verilog latch) and see what cells yosys infers
<cr1901_modern>
One of them was a mux w/ feedback
<cr1901_modern>
I think
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<maikmerten>
hmmm... did something significant change within the last two weeks regarding yosys and nextpnr for the iCE40? My SoC went from ~2500 to ~3000 LCs, but f_max increased from ~35 MHz to ~40 MHz
<maikmerten>
so that's quite something
<tnt>
-relut was enabled by default yesterday.
<tnt>
but ... I wouldn't expect that from it.
<maikmerten>
ah, interesting
<maikmerten>
is there a description on what it does?