<tpb>
Title: database for ECP5 CABGA381 is missing pin U3 · Issue #75 · SymbiFlow/prjtrellis · GitHub (at nuget.pkg.github.com)
<daveshah>
For the flash clock you should use the USRMCLK primitive anyway
<daveshah>
I'm not even sure if Diamond allows you to use the clock as a normal IO or forces you to use the primitive too
<trmm>
ERROR: No wire found for port USRMCLKTS on destination cell usrmclk_inst.
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<daveshah>
Is your trellis and nextpnr up to date?
<daveshah>
This was fixed fairly recently
<trmm>
last pulled in April, so I'll do an update
<daveshah>
Just updating nextpnr should be fine
<daveshah>
Think I fixed the nextpnr side sometime in may
<trmm>
trellis was up to date since you just merged my most recent pr. I'm rebuilding nextpnr now
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<trmm>
Is generating the chipdb bba files supposed to consume all physical memory in the known universe?
<tnt>
trmm: no ... just a few G
<daveshah>
There was a patch by whitequark recently to serialise building them
<trmm>
finally made it past the 85k file without triggering the oom. make -j8 was a mistake in this case...
<daveshah>
This is exactly what that patch was supposed to fix
<trmm>
ok, that fixed the USRMCLKTS issue
<pepijndevos_>
ZirconiumX, PCB has shipped!
<ZirconiumX>
pepijndevos_: and now in a month you'll find out you fucked up
<ZirconiumX>
Did you add a ground plane?
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<pepijndevos_>
ZirconiumX, yes I did. It's all 2 layer through hole stuff, so there is a lot that can be fixed.
<ZirconiumX>
I still think you should learn manual routing
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<pepijndevos_>
I've routed some fairly big 2 and 4 layer PCBs, and it's my least favourite part of electronic design. That moment where you're just staring hopelessly at a giant ratsnest... I'm sure it gets better with experience, I've seen some pretty amazing routing jobs.
<daveshah>
Personally I find routing quite relaxing
<pepijndevos_>
But for this project the whole point of it is kinda the automation IMO. Ideally I'd just compile directly to PCB. I wonder if nextpnr could help here...
<daveshah>
No, nextpnr is designed for highly constrained applications (i.e. FPGAs). It would be no good for ASICs let alone PCBs
<pepijndevos_>
I've explained pcb layout to people as connect the dots for grownups.
<pepijndevos_>
So how does ASIC place and route work?
<daveshah>
Placement isn't that different, just with free choice of location rather than fixex
<daveshah>
*fixed
<daveshah>
Routing I don't know the details but presumably similar enough to a PCB
<pepijndevos_>
But I assume for the amount of transistors in a modern chip there is a lot less manual work than typical PCB layout... or ASIC design is a special kind of hell I don't want to end up in.
<daveshah>
Yes, most general ASIC routing is automated afaik
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<daveshah>
But I suspect some of the standard cells are routed by hand
<pepijndevos_>
Sure
<daveshah>
the routing between those cells wouldn't usually be by hand
<pepijndevos_>
So is there any oss asic pnr yet? Or do you feed the yosys netlist into commercial tools?
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<trmm>
Thanks for the help with the ecp5 USRMCLK issue. The tinyfpga bootloader now works on the ulx3s board, which is so much faster than the bitbang JTAG
<cr1901_modern>
oh nice!
<trmm>
(The FTDI used by ujprog has only 3 megabaud link and requires sending 16 bytes for every byte of the bitstream, so it is very slow)
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<cr1901_modern>
I'd like to see more direct USB connections to FPGAs even if it's limited to 1.1
<cr1901_modern>
err Full Speed*
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<trmm>
the tinyfpga-ex has all of the USB-C pins connected. I wonder how well that will work in practice
<trmm>
(or if everyone will just use the USB 2 pins)
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