<pepijndevos_>
Could anyone knowleable weigh in on how to implement module instantiation in a VHDL frontend? https://gitter.im/ghdl1/Lobby
<tpb>
Title: ghdl1/Lobby - Gitter (at gitter.im)
<pepijndevos_>
I think the current approach is to just synthesize the whole hierarchy in ghdl, but I don't think this allows using hardware primitives or mixing vhdl and verilog.
<pepijndevos_>
If I load a verilog file that references another, it just puts that in as a cell. Is there any extra work required on the ghdl side to do that, or as soon as a module is in ilang all is good and hierarchy will be handled by yosys?
<pepijndevos_>
How is this handled around implementations? In vhdl an entity can have multiple implementations that you can select.
<daveshah>
I don't know about implementations
<daveshah>
But the problem is parameterisable modules
<daveshah>
At the moment read_verilog stores the Verilog AST as well as creating RTLIL
<daveshah>
If the hierarchy command encounters an instance of a module with non-default parameters (and a set of parameters not seen before), then it will rerun elaboration with those parameters
<daveshah>
If you only want to handle VHDL instantiating Verilog modules or blackbox cells (eg FPGA cell instantiation)
<daveshah>
Then elaborating the whole hierarchy in ghdl and leaving unknown modules as blackbox cell instantiations would work
<daveshah>
This wouldn't handle the case of a Verilog module instantiating a VHDL module though
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<pepijndevos_>
daveshah, ah thanks. Is that how verific does it as well?
<pepijndevos_>
ZirconiumX, I can now generate my PWM pcb from VHDL, except it adds a ton of buffer chips. So that's good progress, but it'd be nice if we could tell ABC to not do that.
<pepijndevos_>
It's weird that it adds more of them than the same code in verilog
<ZirconiumX>
Hmm...
<pepijndevos_>
Looking at "show" they are all on the reset lines in this case, but not on the clock. Hmmm indeed
<pepijndevos_>
The hacky solution is of course to do what you suggested and just short them when generating the kicad netlist. Or maybe we could make a techmap that is just a wire.