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<somlo>
daveshah: I think I'm either doing something wrong, or hitting some sort of regression; with the latest yosys/trellis/nextpnr I built over the weekend, the bitstream I'm sending to my ecp5 5g versa just doesn't work
<somlo>
so I'm going to go back and build the versions I had from mid-May, and try to work my way back up to date from there
<somlo>
but wanted to check with you in case this rings a bell... :)
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<somlo>
daveshah: got lucky, only had to downgrade yosys (to the prevous snapshot I had used, c907899) and my stuff started working again
<somlo>
didn't have to go back to May with trellis and nextpnr, whew! :)
<somlo>
is yosys bisect-friendly? I could probably try that if I'm not likely to land on a bunch of intermediate commits where I can't test because of breakage unrelated to what I'm hunting for...
<tpb>
Title: ecp5: Improve mapping of $alu when BI is used · YosysHQ/yosys@a0d3d2b · GitHub (at github.com)
<daveshah>
The second is the ABC9 changes, which I wouldn't attempt to revert but instead try the 0.9 release candidate branch which excludes them
<daveshah>
If neither of those are the problem them bisection would be needed
<daveshah>
I'm not sure how bisect will go with the big ABC9 PR
<somlo>
that's what I was wondering about, chances of landing on random commits where I'll end up encountering unrelated trouble to what I'm hunting for :)
<benreynwar>
ZipCPU: Is there a way to add an 'assume' into my VHDL code? Currently I'm putting them in the top SV wrapper, but it'd be nice to be able to able to put them in the design files too.
<somlo>
so, low hanging fruit first -- $alu mapping, then go from there :)
<somlo>
I'll report back on how that went...
<ZipCPU>
Hello, benreynwar!
<ZipCPU>
There is no way to place either assertion nor assumption into any VHDL code.
<benreynwar>
Using standard VHDL assertions seems to work, but I hadn't found a way to use assumptions yet.
<ZipCPU>
Ok, assertions work ... I had a faint memory of one working while the other did not ...
<benreynwar>
ZipCPU: I kind of figured it wasn't possible, but thought I should ask before going to the effort of making a workaround. Thanks!
<ZipCPU>
That's why, in the VHDL course I teach, we do all the formal verification work itself in Verilog
<benreynwar>
I was thinking of replacing submodules that have been verified already with stubs that just contain assumptions corresponding to the verified assertions. It would have been nice to be able to write those stubs in VHDL since the SV/VHDL interfaces get messy. I'll probably just convert the assumptions into output bits that get sent to the top-level SV and then write the assumption there.
<ZipCPU>
That'd work
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<daveshah>
benreynwar: I think we looked into the possibility of setting an attribute on a VHDL assert to turn it into an assume for formal, but hit a limitation somewhere
<daveshah>
This is still something that I hope we'll get working at some point, it should preserve correct simulation behaviour for assumes too
<daveshah>
Hierarchical references into the VHDL from SV should work, if you want to avoid adding outputs
<benreynwar>
daveshah: That's a good idea! Thanks.
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