clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<promach> ZipCPU: hmm... poor man sequence method in your article does not help much in this case
<promach> it seems like the poor man method might not be able to achieve what I try to achieve
<promach> wait, it is doable
<tpb> Title: D flip-flop with asynchronous reset · GitHub (at gist.github.com)
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<ZipCPU> promach: That's the same thing I've been explaining to you for days. Because the asynchronous reset is assumed to be dropped just before the clock edge. The two are race conditions against each other.
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<promach> ZipCPU: so, enable signal is actually high during posedge clk ?
<ZipCPU> "<ZipCPU> promach: That's the same thing I've been explaining to you for days. Because the asynchronous reset is assumed to be dropped just before the clock edge. The two are race conditions against each other."
<promach> I saw that
<promach> in the online log
<promach> ZipCPU: so, enable signal is actually high during posedge clk ?
<promach> otherwise line 27 will not be executed
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<promach> ZipCPU: manipulating the enable signal input will also not solve such issue
<promach> I am afraid
<promach> this is a delta race condition
<promach> do I need to extend the enable signal ?
<promach> as well as the reset signal ?
<ZipCPU> if (reset) assume(!enable)
<promach> hmm...
<promach> if (reset_wsync) assume(!enable)
<promach> because of always_ff @(posedge write_clk, posedge reset_wsync)
<promach> but this is not reliable since this is nly for formal verification
<promach> and we only do it after the reset synchronizer
<promach> ZipCPU: this is a bit tricky to solve
<promach> As for "if (reset) assume(!enable)" , this is not helpful too since we could have vastly different clocks speed
<promach> this is why we have afifo instead of cheap, conventional synchronizer pair
<promach> ZipCPU: what do you think ?
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<bwidawsk> so would anyone be opposed to having yosys catch SIGINT and ignoring it when in interactive mode?
<bwidawsk> I'd be happy to write the patch
<ZirconiumX> Maybe post an RFC issue in GitHub
<ZirconiumX> I have something I'd like to add to Yosys, too, since it seems to be a common enough idiom
<bwidawsk> ZirconiumX› okay, writing the RFC now
<ZirconiumX> (namely, adding a parameter to the $pos cell to round the output width to a given multiple of N)
<ZirconiumX> (which I'm sure daveshah would like)
<tpb> Title: RFC: Ignore SIGINT in interactive mode · Issue #1157 · YosysHQ/yosys · GitHub (at github.com)
<ZirconiumX> bwidawsk: 👍
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<bwidawsk> would also be nice if long output invoked the pager
<ZipCPU> Why not just use "tee" to send it to a file you can then run the pager on?
<tnt> bwidawsk: sigint is ctrl-c right ? why ignore it ?
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<ZirconiumX> tnt: in interactive mode
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<tnt> ZirconiumX: yeah, I got that, but I still want to easily kill yosys (or at the very least the running command).
<tnt> ZirconiumX: like ... when yosys mis-understood a ram inferrance and starts generating millions of FFs ...
<ZirconiumX> Then we can make ^C while executing a command abort it, perhaps?
<ZirconiumX> I'm not sure if the current architecture of Yosys permits that though
<tnt> sure, that'd be fine (even better than killall), but no idea how easy / hard it'd be ...
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<tnt> longjmp :p
<ZirconiumX> I'd actually use threading here, I think
<ZirconiumX> Running a command spawns a thread to execute it
<daveshah> You'd have to have the command operate on a copy of the netlist structure then
<daveshah> Otherwise things would be inconsistent when you terminated the command
<daveshah> And that would significantly increase memory usage on some big designs (where the netlist can be several GB)
<ZirconiumX> I don't think setjmp/longjmp would be much better in that instance
<ZirconiumX> daveshah: actually, couldn't you get away with copy-on-write here?
<ZirconiumX> It might not be ideal, but it would be consistent
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