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<FSM_Dude>
Hey! Is this the right place to ask for help with Yosys? I'm using it for my studies, but I encounter some problem.
<sorear>
yes
<FSM_Dude>
Great! I already asked the question on SO, but did not have any luck with getting an answer there. I'm quite new to it, and I try to alter the FSM in the fsm_recode pass. If I do so, later on in the fsm_map pass yosys stops because an assertions is violated...
<tpb>
Title: c++ - Yosys: How to correctly add states and transitions to fsm during fsm_recode pass? - Stack Overflow (at stackoverflow.com)
<FSM_Dude>
Yes, that one.
<FSM_Dude>
I managed to get rid of the assertion in a nasty way, but that only made thing worse. Once I ran abc and dfflibmap it showed me that there were 0 gates and 0 wires...
<FSM_Dude>
What Im trying to do, is add redundant states to the fsm. Afterwards I want to see the area of the design. This way I can compare the overhead generated by the added redundancy
<ZirconiumX>
You shouldn't need to hack into Yosys for it
<ZirconiumX>
AFAIK, it won't prune states that are used
<ZirconiumX>
So if you have a one-hot state and then add a wildcard state at the end which does something, I think it'll handle that reasonably efficiently
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<FSM_Dude>
I don't follow, sorry
<pepijndevos>
The symbiyosys docs mention only Z3 is mandatory, but say yices is the default prover... what's the deal there?
<FSM_Dude>
ZirconiumX, this https://imgur.com/a/NiVJafL is basically what I try to achieve within the fsm_recode pass of Yosys
<tpb>
Title: Imgur: The magic of the Internet (at imgur.com)
<FSM_Dude>
Would it be possible to add something like this to Yosys? Or is it impossible to alter the fsm within the c++ code?
<pepijndevos>
FSM_Dude, you're actually patching yosys to support a new type of FSM recoding?
<FSM_Dude>
I try to yes :)
<FSM_Dude>
I try to implement some fault tolerance into the FSM, and then analyse the overhead in terms of area etc
<FSM_Dude>
Just for my own research at uni
<FSM_Dude>
Now I'm wondering if it's even possible with Yosys lol
<pepijndevos>
That's super cool
<daveshah>
I expect the problem is the size of `state_onehot` is wrong
<daveshah>
You would need to look into where that is set, and perhaps resize it
<FSM_Dude>
daveshah, indeed. I think I need to resize some stuff. Also the fsm_data.copy_from_cell() function has some boundaries on the state_in and state_out of the transitions...
<daveshah>
Yeah, I'm afraid I don't know the fsm stuff in Yosys well enough to help with the details
<FSM_Dude>
Hmm okay! Thanks for the tip tho!
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<FSM_Dude>
daveshah, that seemed to have fixed it :)
<FSM_Dude>
Now onto the next problem I face haha
<FSM_Dude>
Thanks a lot!
<FSM_Dude>
27. Executing ABC pass (technology mapping using ABC).27.1. Extracting gate netlist of module `\test' to `<abc-temp-dir>/input.blif'..Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.Don't call ABC as there is nothing to map.Removing temp directory.
<FSM_Dude>
Guess I have a bigger problem than just the assertion lol
<daveshah>
`dump` and `show` are always helpful
<pepijndevos>
In my experience, when you connect something wrong, Yosys is more than happy to optimize away the disconnected logic haha
<FSM_Dude>
Thanks Im gonna have a look!
<FSM_Dude>
pepijndevos Hopefully my redundant states wont be optimized away... :P
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<cr1901_modern>
It is a rite of passage to play a fun game of "guess why the FPGA synthesizer optimized away my whole design"
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<GenTooMan>
cr1901_modern I am glad I got that out of my system several weeks ago I suppose.
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<daveshah>
It shows how easy it is to determine a lack of side effects in hardware, tbh
<daveshah>
Software compilers tend to be much less keen/able to optimise large chunks of code away