clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
tpb has quit [Remote host closed the connection]
tpb has joined #yosys
rohitksingh has joined #yosys
X-Scale` has joined #yosys
X-Scale has quit [Ping timeout: 265 seconds]
X-Scale` is now known as X-Scale
rohitksingh has quit [Ping timeout: 276 seconds]
PyroPeter has quit [Ping timeout: 276 seconds]
ZipCPU has quit [Quit: ZNC 1.6.4 - http://znc.in]
ZipCPU has joined #yosys
pie__ has quit [Ping timeout: 245 seconds]
rohitksingh has joined #yosys
citypw has joined #yosys
pie_ has joined #yosys
rohitksingh has quit [Ping timeout: 245 seconds]
_whitelogger has joined #yosys
Jybz has joined #yosys
citypw has quit [Remote host closed the connection]
pie_ has quit [Ping timeout: 276 seconds]
MrBismuth has quit [Ping timeout: 245 seconds]
MrBismuth has joined #yosys
Jybz has quit [Quit: Konversation terminated!]
dys has quit [Ping timeout: 276 seconds]
pie_ has joined #yosys
smarter has quit [Remote host closed the connection]
vup2 has quit [Quit: No Ping reply in 210 seconds.]
TD-Linux has quit [Ping timeout: 245 seconds]
smarter has joined #yosys
Kokjo has quit [Ping timeout: 245 seconds]
vup has joined #yosys
gmc has quit [Remote host closed the connection]
TD-Linux has joined #yosys
Spida has quit [Ping timeout: 245 seconds]
gmc has joined #yosys
Spida has joined #yosys
pepijndevos has quit [Ping timeout: 240 seconds]
pepijndevos has joined #yosys
craigo has quit [Quit: leaving]
cr1901_modern has quit [Ping timeout: 240 seconds]
daveshah has quit [Excess Flood]
daveshah has joined #yosys
emeb has joined #yosys
whitequark has joined #yosys
<whitequark> 18:23 <rjo> Well. It doesn't do anything on ice40 because the parameter is ignored by nextpnr...
<whitequark> i would suggest filing a nextpnr bug
<daveshah> A bug was filed and the issue was fixed :)
<whitequark> oh oops, i should've checked.
<emily> daveshah: your latency-to-merged-fix is truly impressive
<emily> I felt guilty throwing up a 10k line RTLIL tarball
<whitequark> ZirconiumX: re: flowmap crash
<whitequark> have you seen the bugpoint pass?
<daveshah> These small things are usually easier to fix there and then rather than put on the todo list
<ZirconiumX> whitequark: I was using that very pass to try to find it
<ZirconiumX> Unfortunately because flowmap -relax takes forever I didn't get very far with it before turning my computer off for the night
<whitequark> hm
<whitequark> it should not take forever
<ZirconiumX> (metaphorically)
<whitequark> it's polynomial complexity in theory, and should be pretty fast in practice
<whitequark> ah
<ZirconiumX> It's "I just turned Yosys into Quartus" speed
<whitequark> hmmm
<whitequark> still seems like a problem
<whitequark> flowmap *ought* to be fast. faster than abc in some cases, even
<ZirconiumX> My experience has been the very opposite, sadly.
<whitequark> then that seems like a bug
<whitequark> that said, i haven't had time to work on flowmap much
<ZirconiumX> So, my benchmark here is aoR3000
<ZirconiumX> Which is a MIPS R3000 softcore
<whitequark> that's pretty huge
<whitequark> i've never tested flowmap on anything larger than picorv32
<ZirconiumX> Using my experimental Cyclone synthesis script, Yosys takes 35.87 seconds clock time to build it
<ZirconiumX> s/build/synthesise/
<ZirconiumX> Yosys says most of the CPU time is spent in techmap there
<daveshah> Often the case
<ZirconiumX> Well I've got to spend a lot of time renaming cells, but that's just life
<ZirconiumX> Yaaay Quartus...
<ZirconiumX> whitequark: It spends a very long time labelling cells
<whitequark> labelling?
<whitequark> oh, interesting
<whitequark> that seems like a clear bug
<ZirconiumX> So, that was 2m57.914s to build the same code
<ZirconiumX> Yosys says 154 seconds of the 165 seconds of CPU time was spent in flowmap
<ZirconiumX> And it leaks cells to boot.
<whitequark> leaks cells?
<ZirconiumX> When it fails to map a cell I ask it to map
<ZirconiumX> I call that a cell leak
<whitequark> ah
<ZirconiumX> https://pastebin.com/vaRCJ1fv <-- e.g. these $_AND_ cells should be LUTs
<whitequark> which cells specifically?
<whitequark> aha
<whitequark> seems clearly broken
<ZirconiumX> flowmap -maxlut 6 -cells $_AND_,$_MUX_,$_NOT_,$_OR_,$_XOR_
<whitequark> yeah that should work
<ZirconiumX> And then if I specify -relax, well
<ZirconiumX> Just hit enter
<ZirconiumX> I'll let you know the error message in about fifteen minutes or so
<whitequark> right, i suspect one problem is that it doesn't partition the graph currently
<ZirconiumX> While this runs I guess I'll add differential I/O for vendor.altera
<ZirconiumX> whitequark: ERROR: Assert `(int)lut_edges_bw[succ].size() < order' failed in passes/techmap/flowmap.cc:829.
<ZirconiumX> 2m47.232s
<whitequark> interesting
<Ultrasauce> <ZirconiumX> It's "I just turned Yosys into Quartus" speed
<Ultrasauce> ah yes this will go well with the license server PR im writing
<ZirconiumX> You're welcome, Ultrasauce :P
<daveshah> Well, there's a version of Yosys with a license manager already
<daveshah> albeit somewhat nicer than flexlm
* whitequark senses a conflict of interest within
<ZirconiumX> As a side note I'm still highly confused about Yosys BRAM parameters, which is why there's a $__MISTRAL_MLAB leaking too
cr1901_modern has joined #yosys
<ZirconiumX> Well, bugpoint is slowly progressing
<ZirconiumX> Would be nice if the crash didn't take yonks to occur
<whitequark> the idea behind bugpoint (the LLVM pass) is that CPU time is much cheaper than engineer time
<whitequark> it was written by Google originally I think.
<whitequark> so they can just throw stuff at some compute and forget about it.
alexhw has quit [Remote host closed the connection]
alexhw has joined #yosys
<emily> unfortunately, people have to pay the same amount for all our time
promach has joined #yosys
<ZirconiumX> whitequark: So I wasn't specific enough with my grep
<ZirconiumX> ERROR: Assert `lut_edges_fw[maybe_mergeable_pair.first][maybe_mergeable_pair.second]' failed in passes/techmap/flowmap.cc:1131
<ZirconiumX> Assert `current_val[i].wire != NULL || current_val[i] == value.bits[i]' failed in ./kernel/consteval.h:79
<whitequark> hm
<ZirconiumX> So, I was kinda dumb, but oh well
<ZirconiumX> I found a completely unrelated bug
<ZirconiumX> yay
rohitksingh has joined #yosys
Jybz has joined #yosys
rohitksingh has quit [Ping timeout: 245 seconds]
rohitksingh has joined #yosys
pie_ has quit [Ping timeout: 276 seconds]
Jybz has quit [Quit: Konversation terminated!]
rohitksingh has quit [Ping timeout: 240 seconds]
attie has joined #yosys
attie has quit [Client Quit]
pie_ has joined #yosys
rohitksingh has joined #yosys
attie has joined #yosys
rohitksingh has quit [Ping timeout: 265 seconds]
rohitksingh has joined #yosys
emeb_mac has joined #yosys
gnufan_home has joined #yosys
rohitksingh has quit [Ping timeout: 265 seconds]
attie has quit [Ping timeout: 245 seconds]
attie has joined #yosys
<janrinze> nextpnr-ecp5 gives me results from 55 MHz up to 74 Mhz for the same design in different runs with -r enabled
<janrinze> any clue on how to get the most out of nextpnr?
<ZirconiumX> janrinze: The thing about basically all PnR algorithms is that they're probabilistic
<ZirconiumX> There is no way to "get the most out of nextpnr" other than to keep rolling the dice until you get lucky
<whitequark> that's not entirely true
<whitequark> you could make a fully analytical pnr
<ZirconiumX> I'm pretty sure PnR is NP though, right?
<whitequark> if you want to do it optimally, yes
<emily> there are two wolves in my brain. one of them thinks placing should be entirely analytic. the other is mumbling something about neural net pnr
<whitequark> but you don't need to do it optimally, do you? e.g. you can compute a series of approximate solutions that would converge to the optimal one at some point, and just never actually do it
<janrinze> I'm thinking about a loop that reruns nextpnr several times until it gets a good result. It might be interesting to optimize that method by only keeping the fastest result
<whitequark> interestingly, nextpnr became much faster with a semi-analytical placer
<janrinze> i just had two hits in a row where the results are >72 MHz. lucky streak?
<sorear> there’s no reason in principle for a deterministic approximation algorithm to be impossible
<janrinze> sorear: but there is also no reason for that algorithm to produce the most optimal result..
<janrinze> sorear: it's about having a deteministic algorthm that also finds the optimal result.
<whitequark> janrinze: it's not possible to have optimal pnr
<whitequark> (for any realistic fpga and design)
<whitequark> just like it's not possible to emit optimal machine code
<whitequark> (for any realistic cpu and program)
<janrinze> whitequark: optimal != perfect
<whitequark> i'm not sure what you mean by "perfect" but if the goal of a pnr algorithm is to optimize your design for speed, "optimal" means "highest possible fmax"
<janrinze> whitequark: optimal means the configuration that is the best fit within the possible solutions the system can provide.
<whitequark> yes. that's the same thing.
<janrinze> highest possible fmax could be achieved in many ways we don't even have knowledge of today.
<whitequark> for many of my designs i don't even care what fmax is as long as it meets the constraints
<ZirconiumX> Generally there's a "fast enough" point, yeah.
<whitequark> if the constraints are external and static, i actually *don't* want pnr to try harder. i just want it to meet my 48 MHz or whatever as quickly as possible
<ZirconiumX> For all the shit I give Quartus, it's pretty good at that
<janrinze> true, that. But it's a bit of a Pita if that fmax is only achieved 1 out of 10 runs.
<whitequark> that's certainly true
<whitequark> maybe there should be some sort of flag for nextpnr that says "if you didn't meet constraints, rip up and try again"
<janrinze> I have 3 results that are >74 MHz. constraint is 72 Mhz. but often it only reaches 56 or 58 MHz. The variation is quite a lot. ( 18/56 => 32% )
<whitequark> isn't it 22%
<whitequark> still a lot
<whitequark> probably stuck in a local minimum of some sort
pepijndevos has quit [Ping timeout: 246 seconds]
gnufan_home has quit [Quit: Leaving.]
attie has quit [Read error: Connection reset by peer]
pepijndevos has joined #yosys
attie has joined #yosys
<janrinze> I do think that it's doing a great job though.
Ekho has joined #yosys
<promach> For nextPnR-ice40 , How to generate the json file for a particular verilog code design ?