clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<pepijndevos> oh nooo, I'm doing something silly
<pepijndevos> Traceback (most recent call last):
<pepijndevos> File "/home/pepijn/code/nextpnr/ecp5/trellis_import.py", line 22, in <module>
<pepijndevos> import database
<pepijndevos> ModuleNotFoundError: No module named 'database'
<pepijndevos> why is it trying to use prjtrellis from my home dir?
<daveshah> It isn't, that's the path to the file in nextpnr
<daveshah> make sure TRELLIS_INSTALL_PREFIX is being passed to cmake
<pepijndevos> yay
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<thardin> is it possible to do preprocessor-y things with yosys?
<thardin> like -DFEATURE_X=1
<thardin> I have a design that works slightly different on artix-7 and ice40. would be nice to be able to build the same code for both
<Lofty> thardin: add a space between the -D and the define
<Lofty> But yeah, `read_verilog -D FOO=1` works
<Lofty> And you can also pass it with `yosys -D FOO=1`
<thardin> that's not what the manpage for -D says
<thardin> -D <header_id>[:<filename>] dump the design when printing the specified log header to a file. yosys_dump_<header_id>.il is used as filename if none is specified. Use 'ALL' as <header_id> to dump at every header.
<thardin> but now I see "help read_verilog" shows what you say. thanks, I should have thought of checking there too
<Lofty> -D <macro>[=<value>]
<Lofty> set the specified Verilog define (via "read -define")
<Lofty> (for `yosys -D`)
<Lofty> -Dname[=definition]
<Lofty> define the preprocessor symbol 'name' and set its optional value
<Lofty> 'definition'
<Lofty> (for `read_verilog -D`)
<thardin> strange
<thardin> this is with Yosys 0.9+1706 (git sha1 a0cc795e, gcc 6.3.1 -fPIC -Os)
<Lofty> `yosys -h`
<Lofty> It's near the bottom
<thardin> uhhh
<thardin> so
<thardin> the manpage and --help don't agree
<Lofty> Yosys does not have a manpage
<thardin> I can "man yosys" just fine
<Lofty> I can't
<Lofty> There is no manual page in the Yosys source that I can find
<daveshah> Yeah I don't seem to have one either
<daveshah> must be some distro-provided thing or something
<thardin> I was just about to say
<thardin> I installed debian's version but then compiled my own
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<Lofty> Does anybody know of a hack to obtain a unique identifier - or even just the cell name - in techmap?
<Lofty> For context: Quartus wants a "logical RAM name" in the memory cells
<Lofty> I initially set this to be a constant string and assumed Quartus would be smart enough
<Lofty> But no, it wants a unique identifier
<Lofty> And the only alternative I can think of is manually fiddling with RTLIL for this
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