<tpb>
Title: Language guide nMigen toolchain 0.3.dev143 documentation (at nmigen.info)
<Lofty>
whitequark: I'm pretty sure pysim will also break on a 208GiB Signal
<whitequark>
not necessarily, actually
<whitequark>
as long as you only use the low bits i think it might be f... ah no
<whitequark>
the mask will be that long
<whitequark>
it will
<Lofty>
So nMigen probably also has some point where it can't feasibly represent some signals.
<whitequark>
yep
<whitequark>
it already rejects signals over 16 Mbits in back.rtlil
<whitequark>
Verilog only requires support for 64 Kbits, and Yosys flat out breaks on 4 Gbits (the lexer has UB at that point)
<whitequark>
(or had, I might have fixed it)
<whitequark>
I'm gonna lower that to 1 Mbit, I think
<daveshah>
I would suggest a 64kbit limit for now
<whitequark>
daveshah: thanks, will do
<daveshah>
iirc even 128kbit ish was killing performance in some cases
<whitequark>
oh yeah I misremembered
<whitequark>
hm, wait
<mwk>
hmm
<mwk>
how are things like memory init values handled?
<mwk>
these could very reasonably grow Big
<whitequark>
in yosys or?
<daveshah>
oh yeah, hmm
<mwk>
nmigen
<whitequark>
nmigen emits a single $meminit cell with \DATA connected immediately to a constant
<whitequark>
so no wires there
<mwk>
alright, good enough then
<mwk>
(for nmigen at least; yosys still make a SigSpec out of it, hmmmm)
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<mwk>
how are $meminit with non-const ADDR / DATA useful?
<whitequark>
mwk: lets you do things like mem[0] = 1+1;
<whitequark>
without having to evaluate it in the frontend, i gess
<mwk>
oh, hm
<mwk>
but doesn't the frontend already have to know how to evaluate const expressions for things like cell parameters anyway?
<whitequark>
no idea
<daveshah>
yeah, it does
<daveshah>
also for things like wire widths
<mwk>
... petition to change it to parameters instead of ports during memory inference redesign?
<daveshah>
don't have an immediate objection but there may be a subtlety I'm missing
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<emeb>
Am I missing something or are the ECP5 PLLs and other clock management cells not yet supported by yosys?
<daveshah>
?
<daveshah>
They are supported fine
<emeb>
Looking through cells_sim.v I don't see the instantiation templates.
<daveshah>
They are in cells_bb.v
<emeb>
thx
<Lofty>
daveshah: are PLLs actually simulatable?
<Lofty>
It seems difficult to model (to me)
<emeb>
It can be done, but it's usually a hack in verilog. I've done it by making a behavioral model of what a PLL does, but it's really hard to match the actual loop dynamics.
<emeb>
Hmm... when I try to instantiate the EHXPLL yosys is happy and nextpnr seems fine through most of the process but then throws an assertion during routing.
<emeb>
Terminate called after throwing an instance of 'nextpnr_ecp5::assertion_failure'