kraiskil has quit [Read error: Connection reset by peer]
maartenBE has joined #yosys
Degi has quit [Ping timeout: 240 seconds]
Degi has joined #yosys
citypw has joined #yosys
jeanthom has quit [Ping timeout: 256 seconds]
craigo has quit [Ping timeout: 246 seconds]
ross_s has quit [Ping timeout: 246 seconds]
emeb_mac has quit [Quit: Leaving.]
Thorn has quit [Ping timeout: 265 seconds]
Thorn has joined #yosys
jakobwenzel has joined #yosys
jakobwenzel has quit [Ping timeout: 272 seconds]
jakobwenzel has joined #yosys
dys has joined #yosys
<az0re>
So, before I go check for myself, does anyone know off the top of their head how would a Verilog always block with complete case statement get translated to RTLIL? Would it make a mux tree?
<az0re>
assuming `proc; opt; techmap` were called after `read_verilog`
<az0re>
Or would it instantiate, say, pmuxes with $eq cells on the select lines?
Asu has joined #yosys
<Lofty>
az0re: a complete case is probably turned into the latter
<Lofty>
Incomplete cases would probably be mux trees due to the Verilog standard requiring ordering
X-Scale` has joined #yosys
X-Scale has quit [Ping timeout: 260 seconds]
X-Scale` is now known as X-Scale
X-Scale has quit [Ping timeout: 246 seconds]
X-Scale` has joined #yosys
X-Scale` is now known as X-Scale
craigo has joined #yosys
Asu is now known as Asuu
kraiskil has joined #yosys
peepsalot has quit [Quit: Connection reset by peep]
peepsalot has joined #yosys
az0re has quit [Ping timeout: 240 seconds]
smarter_ has joined #yosys
y2kbugger_ has joined #yosys
smarter has quit [Ping timeout: 264 seconds]
tlwoerner has quit [Ping timeout: 246 seconds]
Degi has quit [Ping timeout: 246 seconds]
cr1901_modern has quit [Ping timeout: 246 seconds]
y2kbugger has quit [Ping timeout: 246 seconds]
Nazara has quit [Ping timeout: 246 seconds]
Ekho has quit [Remote host closed the connection]
gmc has quit [Ping timeout: 246 seconds]
y2kbugger_ is now known as y2kbugger
mwk has quit [Ping timeout: 246 seconds]
captain_morgan0 has joined #yosys
Degi has joined #yosys
captain_morgan has quit [Ping timeout: 264 seconds]
captain_morgan0 is now known as captain_morgan
Nazara has joined #yosys
mwk has joined #yosys
Forty-3 has quit [Ping timeout: 264 seconds]
gmc has joined #yosys
emeb has joined #yosys
Forty-3 has joined #yosys
Ekho has joined #yosys
az0re has joined #yosys
cvl has joined #yosys
_whitelogger has joined #yosys
citypw has quit [Ping timeout: 240 seconds]
jakobwenzel has quit [Quit: jakobwenzel]
dys has quit [Ping timeout: 240 seconds]
Ristovski has quit [Quit: 0]
cr1901_modern has joined #yosys
Ristovski has joined #yosys
<az0re>
Lofty: Thanks
<Lofty>
np
dys has joined #yosys
tlwoerner has joined #yosys
m_w has joined #yosys
<az0re>
Indeed, it looks like a pmux with $eq cells on the select lines, except for case zero which has $logic_not on the select line
<az0re>
I am a little confused, actually. What exactly is the behavior of pmux?
<az0re>
For each bit i, z[i] = s[i]? b[i] : a[i] ?
<az0re>
No
<az0re>
nvm I found it in the manual
kraiskil has quit [Ping timeout: 256 seconds]
kraiskil has joined #yosys
kraiskil has quit [Ping timeout: 264 seconds]
nengel has quit [Ping timeout: 260 seconds]
emeb_mac has joined #yosys
N2TOH has quit [Read error: Connection reset by peer]
N2TOH has joined #yosys
josi has quit [Quit: Ping timeout (120 seconds)]
josi has joined #yosys
nengel has joined #yosys
Asu has joined #yosys
Asuu has quit [Ping timeout: 260 seconds]
<mwk>
pepijndevos: ping
<Lofty>
I don't think pepijndevos will be around at this hour, mwk
<mwk>
well I need a gowin question answered...
<Lofty>
About DFFs?
<mwk>
yes
<mwk>
the one I asked a few days ago
<Lofty>
... Lemme ping him on Twitter
emeb_mac has quit [Ping timeout: 246 seconds]
emeb has quit [Ping timeout: 256 seconds]
emeb_mac has joined #yosys
emeb has joined #yosys
Asu has quit [Remote host closed the connection]
kraiskil has joined #yosys
maartenBE has quit [Ping timeout: 240 seconds]
maartenBE has joined #yosys
<ananan>
how do i get yosys to generate the hierarchy if i used -defer in read_verilog?
<ananan>
i tried doing `hierarchy` and `hierarchy -check -top top` but neither worked
<ananan>
(after that is `synth_ecp5 -json json.out -top top` and it generates a json with no modules)