clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<nmz787> can I include/import/inherit a PCF in my PCF
<nmz787> like, I have the icebreaker.pcf... but some random VGA test design uses other names for it's TOP module inputs/outputs
<nmz787> I'd rather not have to duplicate+modify icebreaker.pcf for each design I play with
<whitequark> you can wrap the verilog for that vga test design
<whitequark> but in general you should probably duplicate the pcf
<nmz787> wrap the verilog meaning.... explicitly create a top module and instantiate the previously implicit top?
<whitequark> yeah
<nmz787> hrmm
<nmz787> so multiple pins are combined into a bus in the PCF
<nmz787> I'm not sure how to emulate that when instantiating the module, but not having a bus
<nmz787> i.e. set_io RED[1] P1A2; set_io RED[0] P1A1
<nmz787> I guess I might be able to use an array of wires?
<nmz787> it doesn't seem to like this wire RED[3:0] = {P1A4, P1A3, P1A2, P1A1};