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<
tpb >
Title: FOSS FPGA Toolchain Build Script · GitHub (at gist.github.com)
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<
tpb >
Title: nextpnr/CMakeLists.txt at master · YosysHQ/nextpnr · GitHub (at github.com)
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<
cr1901_modern >
err ECP5_CHIPDB*, but it's analogous
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<
whitequark >
cr1901_modern: oh, that's prob a typo
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<
whitequark >
think you can send a PR?
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<
cr1901_modern >
Yes, give me a minute and I will
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<
tpb >
Title: Fix MESSAGE indicating where externally-built .bbas live. by cr1901 · Pull Request #491 · YosysHQ/nextpnr · GitHub (at github.com)
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thardin >
dkozel: haven't looked at gr internals yet, but sounds promising
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<
thardin >
does yosys not implement $fdisplay? I tried enabling systemverilog. no dice
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<
thardin >
I'd like my assertion messages to go to stderr, and/or to show up even with yosys -q
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<
daveshah >
Have you tried $error, outside of a block ?
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<
thardin >
`define assert(signal, value) if (signal !== value) $error({"ASSERTION FAILED: ", `"signal`", " != ", `"value`"});
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<
thardin >
`define assert(cond) if (!(cond)) $error({"ASSERTION FAILED: ", `"cond`"});
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<
thardin >
even simpler
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DaKnig >
can yosys spit out vhdl?
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<
tpb >
Title: Build your own FPGA - Nick's Blog (at blog.notdot.net)
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<
Lofty >
Why stop at that?
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<
Lofty >
I wrote a Yosys script to synthesise Verilog into 74xx logic
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<
tnt >
still waiting for that 7400 riscv :p
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