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<pepijndevos>
If I accumulate a bunch of things with a generate loop, will something in the chain balance the adder tree, or will it become a huge speed bottleneck?
<mwk>
alumacc will make a $macc cell out of it with shitloads of inputs
<mwk>
maccmap will turn it into lots of 3-to-2 adder compression stages, plus an $alu for the final stage
<pepijndevos>
3-to-2 adder compression stages?
<mwk>
hmm, never heard of 3:2 compressor?
<mwk>
*sigh* I cannot seem to find a good reference for it
<pepijndevos>
... maybe... it rings a very remote bell
<mwk>
the idea is that you have 3 numbers to add
<mwk>
so you use a bunch of full adders, but without a carry chain, to turn that into two numbers you have to add
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<pepijndevos>
I remember we once had a random lecture that covered an algorithm for building the most efficient tree of what you call compressors.
<mwk>
the main idea here is that you still have the same amount of full adders, but only the final stage actually needs a carry chain
<pepijndevos>
Something weird where you assigned levels to things and had to combine things from the same levels or something
<mwk>
mhm
<mwk>
sounds like maccmap
<pepijndevos>
I see
<pepijndevos>
Long story short: it will turn into something reasonable
<pepijndevos>
thanks :))
<mwk>
... more or less
<mwk>
there's a bunch of ways that maccmap could be improved
<mwk>
but eh
<mwk>
the same could be said about every single part of yosys
<pepijndevos>
hrm
<mwk>
eg. for a LUT6-based architecture it's quite likely that using 5:3 or 6:3 compressors would be a better idea
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<pepijndevos>
hm yea you could not actually use ALU hardware for the full adders, because at least on gowin you can't access the carry chain in regular logic.
<mwk>
oh it doesn't
<mwk>
it only uses the carry chain *for the final stage*
<mwk>
the compression stages are just plain LUTs
<pepijndevos>
right
<mwk>
for gowin, being a LUT4 architecture, 3:2 compressors should actually be optimal