clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<pepijndevos> ahhh, regression time??
<pepijndevos> Warning: Failed to find a route for arc 0 of net $abc$539$auto$alumacc.cc:485:replace_alu$4.CO[21]_new_.
<daveshah> Looks like it
<pepijndevos> The weird thing is I can't find any such net in my input file...
<daveshah> Probably some new carry pattern that nextpnr isn't expected
<daveshah> I can have a look
<pepijndevos> What do you mean? Ah, regression in nextpnr? I was assuming it' my own fault
<pepijndevos> Also: is it intentional that assertions no longer raise python exceptions?
<daveshah> Oh, what arch is this?
<daveshah> That sounds like an issue with the new pybind11 stuff
<tpb> Title: Avoid adding duplicate wires by kbeckmann · Pull Request #13 · YosysHQ/apicula · GitHub (at github.com)
<daveshah> Ahh
<daveshah> I was assuming this was ECP5 for some reason
<pepijndevos> ah no, it's apicula, sorry
<pepijndevos> Does that mean it *is* in fact my own fault?
<daveshah> Probably, unless something else has broken with the pybind11 move
<daveshah> I know the nextpnr-generic example was still working as that was one of our main regression tests for that
<mwk> oh nice, a yosys/nextpnr regression that wasn't me
<pepijndevos> lol
<pepijndevos> So, uh... what does this error indicate? Not really sure where to start looking. Apicula doesn't support ALU or carry at all
<daveshah> That name will just be from Yosys' internal mapping of an adder
<daveshah> The problem is that it has failed to find a route for some reason
<daveshah> --debug --verbose will enable more info on the failed route
<daveshah> there are some ifdefs that can be enabled in the router for even more debugging
<pepijndevos> Ok ill try thanks :)
* pepijndevos waiting 10 minutes for Python to load the wires
<pepijndevos> So at least it looks like looking at the input JSON files it's just a normal wire from a LUT output to another LUT input. Not much special.
<pepijndevos> https://bpa.st/U3LA
<tpb> Title: View paste U3LA (at bpa.st)
<pepijndevos> So it looks like it can't find any route from the LUT output at column 8 to the LUT input in column 9... extremely weird
<daveshah> Are other LUTs routing fine?
<daveshah> Or is this just the first LUT it finds and so the first one that fails?
<pepijndevos> If I understand the output correctly, the first one succeeds, and then the second one fails
<pepijndevos> but the first one is within the same tile
<daveshah> Yep, seems like some routing has gone missing
<pepijndevos> ugh...
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<pepijndevos> I will be sad if it's the PR that worked around the assert problem
<daveshah> Can you create a nextpnr issue for that btw?
<pepijndevos> Oh yea will do
<daveshah> thx
<pepijndevos> ... while I wait for python to load all my wires haha
<daveshah> incidentally, that patch seems like it might not be helping performance wise?
<daveshah> added_wires should be a set not a list, probably
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<pepijndevos> probably
<kbeckmann> ah good catch..
<pepijndevos> I was thingking... I don't remember it being THAT slow
<pepijndevos> lol, it's instant now
<kbeckmann> just as a datapoint in case there is a regression in nextpnr, i was building a design that worked a few days ago, but when i rebuilt it with a brand new yosys/nextpnr it breaks down after a few seconds of runtime. worked fine earlier.
<kbeckmann> cool
<kbeckmann> sorry for the bad code :p
<daveshah> I think this might be something broken in the new pybind11 stuff then
<daveshah> Not sure what though
<kbeckmann> unfortunately i don't have the git hash of the working revision :/
<daveshah> was it before 10 days ago?
<kbeckmann> it was probably around 10 days old give or take.
<pepijndevos> printing all the pips that match the broken net, and I'm too sleepy to see what's going on https://bpa.st/AO5Q
<tpb> Title: View paste AO5Q (at bpa.st)
<pepijndevos> A4 seems to be connected topip R2C9_E251_A4 E251 R2C8_E25 A4 R2C9_A4
<pepijndevos> pip R2C9_E271_A4 E271 R2C8_E27 A4 R2C9_A4
<pepijndevos> But F4 is only on pip R2C8_F4_E240 F4 R2C8_F4 E240 R2C8_E24
<pepijndevos> Maybe my fuzzer broke, I don't know...
<pepijndevos> bleg, good night
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