clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<tnt> Is there a way to guide yosys/abc to use a given cell to synthesize adders ? the cell library has a full adder cell but it's not used for adders when just feeding the liberty file.
<daveshah> nope, abc can't map multi output cells
<daveshah> you can use Yosys' extract_fa and techmap, but then you lose all of the abc optimisations, buffer sizing, timing, et
<daveshah> *etc
<daveshah> the cost of doing that is probably higher than the benefit of using an adder cell, Yosys should use a fairly good algorithm for adders anyway
<Lofty> daveshah: or techmap $alu (though with full adder cells it's a bit questionable)
<daveshah> Yeah, and it still has the same downsides
<daveshah> adder mapping is certainly a lot less important in asic than in fpga
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