clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<scientes> does the nitefury run OK without a heatsink? because it will not fit in my laptop
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<scientes> is there any way to do a self-modifying FPGA?
<scientes> I can imagine some interesting data structures that would enable
<scientes> appears I am not the only one https://patents.google.com/patent/US5838165A/en
<tpb> Title: US5838165A - High performance self modifying on-the-fly alterable logic FPGA, architecture and method - Google Patents (at patents.google.com)
<mwk> scientes: what exactly do you have in mind?
<mwk> there's a thing called partial reconfiguration which kind of counts
<scientes> well the idea I just had would be kinda like a hash table
<strubi> There are some interesting hacks on the xilinx side with partial reconfig on virtex families, but it's been a while. Used to be very complex.
<strubi> nowadays you might wanna do that on a Zynq platform, I guess
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<scientes> yeah this is cool. I was thinking more like a JIT however
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<strubi> if it's gotta be quick, you're better off with your own microcode architecture
<strubi> other than that, could be fun to try running yosys/nextpnr on a zynq platform
<strubi> (one day, when it's supported)
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<lf> what is the way to simulate a gateway that uses ecp5 ressourcen like DP16KD? from what i have read so far i need Diamond and in there i can find or generate the behavior libs. can i then load that into yosys and generate cxxrtl from that?
<daveshah> You would have to use iverilog
<daveshah> the Diamond DP16KD model is non-synthesisable and so can't be used with Yosys/cxxrtl (I doubt it would work well with Verilator either)
<lf> ok so a) see what Diamond has for simulation or b) write my own inplementation?
<daveshah> yes
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