clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<aaaa> hmm alright
<aaaa> the goal was for synthesizing an old retro schematic/transistor netlist into usable verilog for an FPGA
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<Lofty> And, sure, but you need to produce something higher level than that
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