clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<kitten_nb_five> Hell World! I am just beginning to learn Verilog and FPGA-stuff and i really appreciate the FOSS-toolchain. Thank you!
<kitten_nb_five> I have a problem but i am not sure if this is wrong syntax or sth with yosys. Maybe somebody can tell me? [...]
<kitten_nb_five> I have a definition of a module and i want to create an instance of this module with a parameter
<kitten_nb_five> This works/"compiles": mod_div #(.pDivider(25_000_000)) div_slow(.clk(clk_25M), .clk_div(out_slow));
<kitten_nb_five> This gives me an error, so is this valid Verilog or not? mod_div #(parameter pDivider=25_000_000) div_slow(.clk(clk_25M), .clk_div(out_slow));
<tnt> no
<kitten_nb_five> ok, ty!
<kitten_nb_five> Another question if you allow: Is there a way to make yosys return a non-zero exitcode in case of any warnings, like -Werror for the GCC? This would be useful for chaining commands (Linux): yosys ... && nextpnr ...
<tnt> no idea
<tnt> but given some yosys warning are both harmless and hard to get rid of, I'm not sure how useful it'd be in practice.
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<kitten_nb_five> i am really just beginning to use yosys and only had "good"=meaningfull warnings. When writing software i always try to make it compile with -Werror, so i thought this might be a good idea for doing FPGA-stuff to (especially for a total beginner)
<tnt> Yeah, I have the same policy for sw, but AFAIK yosys doesn't have anything like -
<tnt> -Wno-xxx to disable some warnings ...
<tnt> Oh my bad, it does.
<tnt> -e
<tnt> Allows to specify a regulat expression to turn warning into errors. (so you can make a regexp that matches everything ...)
<tnt> it'll stop at the first error though AFAICT.
<kitten_nb_five> ty, i did not see this one in the manual. i will give it a try
<tnt> I read the source code ... not the manual :p
<kitten_nb_five> -e works great!
<kitten_nb_five> yosys -p "synth_ecp5 -json out.json" -q blink.v
<kitten_nb_five> Warning: Wire top.\div_slow.clk is used but has no driver.
<kitten_nb_five> yosys -p "synth_ecp5 -json out.json" -q -e ".*" blink.v
<kitten_nb_five> ERROR: Wire top.\div_slow.clk is used but has no driver.
<kitten_nb_five> ty!
<kitten_nb_five> uh, that should better be ".+"
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<ZipCPU> kitten_nb_five: Consider using verilator -Wall
<kitten_nb_five> i don't know this one, i will look at it. ty.
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