clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
tpb has quit [Remote host closed the connection]
tpb has joined #yosys
_whitelogger has joined #yosys
emeb_mac has quit [Ping timeout: 260 seconds]
emeb_mac has joined #yosys
_whitelogger has joined #yosys
Degi has quit [Ping timeout: 240 seconds]
Degi has joined #yosys
_whitelogger has joined #yosys
citypw has joined #yosys
_whitelogger has joined #yosys
vidbina has joined #yosys
_whitelogger has joined #yosys
FFY00 has quit [Ping timeout: 260 seconds]
FFY00 has joined #yosys
vidbina has quit [Ping timeout: 240 seconds]
citypw has quit [Ping timeout: 240 seconds]
emeb_mac has quit [Quit: Leaving.]
N2TOH has quit [Ping timeout: 260 seconds]
X-Scale has quit [Ping timeout: 240 seconds]
X-Scale` has joined #yosys
X-Scale` is now known as X-Scale
_whitelogger has joined #yosys
az0re has quit [Remote host closed the connection]
az0re has joined #yosys
Asu has joined #yosys
vidbina has joined #yosys
DaKnig has joined #yosys
vidbina has quit [Ping timeout: 258 seconds]
Forty-Bot has quit [Read error: Connection reset by peer]
Forty-Bot has joined #yosys
kristianpaul has quit [Read error: Connection reset by peer]
kristianpaul has joined #yosys
citypw has joined #yosys
vidbina has joined #yosys
citypw has quit [Remote host closed the connection]
citypw has joined #yosys
wiizzard has quit [*.net *.split]
MoeIcenowy has quit [*.net *.split]
MoeIcenowy has joined #yosys
wiizzard has joined #yosys
emeb has joined #yosys
citypw has quit [Ping timeout: 240 seconds]
vidbina has quit [Ping timeout: 260 seconds]
<tnt> :/ Is there something more to do that adding 'multiclock on' in the .sby for riscv formal to behavre properly with @negedge in the design ?
<tnt> without it I get 'FAIL' for the reg_ch0 test. With it on, I get 'PASS' ... but I get PASS also if I voluntarely add a bug in my register implementation so that doesn't inspire much confidence that the testing is working.
<daveshah> You may need to double all the bmc depths too
<daveshah> With multiclock on, it will be two solver steps per clock cycle
<tnt> ok, I doubled `depth` and `skip`
<tnt> Ok, it failed on the purposefully buggy implementation, good first step. Lets see how it does on the (hopefully) correct one.
<tnt> Arf, failed :/
<tnt> And the trace vcd is showing me nothing AFAICT. I mean the register write enable is low for the entire trace so not sure what's it expecting there.
<daveshah> It might be to do with skip and the fact that multiclock gives it the freedom to keep the clock stuck not toggling
<daveshah> You might need to constrain the clock, although this is slightly beyond my formal experience
<tnt> In the vcd at least I see it toggling regularely.
<daveshah> Ah, that probably isn't the problem then
<tnt> Shure SM7b
<tnt> (sorry bad cut & paste ... )
<Lofty> tnt: always preferred the SM57 myself /s
<tnt> :)
N2TOH has joined #yosys
N2TOH_ has joined #yosys
N2TOH has quit [Ping timeout: 240 seconds]
<tnt> ¯\_(ツ)_/¯ I guess the fact it seems to run software just fine will have to be good enough.
emeb_mac has joined #yosys
vidbina has joined #yosys
vidbina has quit [Ping timeout: 272 seconds]
Asuu has joined #yosys
Asu has quit [Ping timeout: 260 seconds]
Asuu has quit [Quit: Konversation terminated!]
Asuu has joined #yosys
Asuu has quit [Ping timeout: 264 seconds]
litghost has quit [Read error: Connection reset by peer]
litghost has joined #yosys
lf has quit [Ping timeout: 260 seconds]
lf has joined #yosys
az0re has quit [Ping timeout: 240 seconds]
emeb has quit [Quit: Leaving.]