clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<Sarayan> Is someone smarter than me capable of running a software simulation of https://github.com/ijor/fx68k ?
<tpb> Title: GitHub - ijor/fx68k: FX68K 68000 cycle accurate SystemVerilog core (at github.com)
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<Lofty> Sarayan: it might simulate under GHDL or something
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<Sarayan> ghdl does vhdl, not system verilog
<Lofty> I got it mixed up with the other m68k core which is VHDL
<Sarayan> there's an other cycle-precise 68k core?
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<Lofty> Sarayan: TG68K. https://opencores.org/projects/tg68
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<tpb> Title: Minimig-AGA_MiSTer/rtl/tg68k at MiSTer · MiSTer-devel/Minimig-AGA_MiSTer · GitHub (at github.com)
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<thardin> is it possible to have input arrays somehow besides flattening?
<thardin> like input [11:0] values [0:3]
<thardin> I tried using systemverilog
<thardin> and using wire instead of input
<Lofty> thardin: what's your use case for that?
<thardin> right now I'm trying to dump some 12-bit values to an LCD as hex
<Sarayan> Lofty: Not cycle-exact, just an inspired reimplementation
<tpb> Title: Is there a way to specify internal pullups for the ICE40 family? · Issue #2354 · YosysHQ/yosys · GitHub (at github.com)
<tpb> Title: nextpnr/ice40.md at master · YosysHQ/nextpnr · GitHub (at github.com)
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<Sarayan> '/lastlog cuavas
<Sarayan> gah
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