clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<thardin> I'm trying to optimize my sine module and yosys is turning my bram into LCs when I invert outputs for 180°-360°
<daveshah> Is the inversion added before the output register by any chance?
<daveshah> Yosys won't retime that away
<thardin> removing the inversion, so that the output is abs(sin(x)) keeps the bram
<thardin> here's an excerpt:
<thardin> wire [SINE_BITS-1:0] lut = sine_lut[xlow[SINE_SZ-2:SINE_SZ-LUT_SZ-1]];
<thardin> assign y = lut ^ (x[SINE_SZ-1] ? 65535 : 0);
<thardin> where y is the output wire
<thardin> ah is there a case where a fake temporary reg is needed?
<thardin> s/there/this/
<daveshah> Yes if you want this to map to BRAM then lut needs to be a reg
<thardin> hmm
<daveshah> clocked by the read clock
<thardin> I can't use bram as a combinatoric LUT?
<daveshah> No
<thardin> sad
<daveshah> If it worked before it was because Yosys was folding in a register from somewhere else
<daveshah> which it can't do with the inversion
<thardin> can't imagine why I couldn't put combinatorics after the output of the bram, but maybe with the surrounding context it becomes impossible
<daveshah> You can do
<daveshah> so long as that output is clocked
<thardin> it is, but in another module. maybe yosys isn't able to see that
<daveshah> It will be able to see that if there is no logic in between
<thardin> aha
<thardin> that explains it :)
<thardin> is this a limitation in yosys or verilog? or both?
<daveshah> In general synthesis tools don't like moving logic around registers
<daveshah> this is usually opt-in as a retiming option, but even then that is to improve perfomance not help extract memories in more cases
<thardin> right, I was about to say
<thardin> this kind of construct would degrade performance
<thardin> and I have plenty of "cycles" available in my little state machine to pipeline things
<thardin> not that my current ADCs and DACs are anywhere near fast enough to exploit this. yet.
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<thardin> hooray, it works
<Lofty> <daveshah> In general synthesis tools don't like moving logic around registers <-- unless you're Quartus, anyway
<daveshah> Retiming is enabled-by-default?
<Lofty> Yep
<Lofty> Though I'm pretty sure it's performed in place and route
<thardin> quadrupled the accuracy of it too
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