clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<benh> Any idea what this means ?
<benh> ERROR: Assert `chunk.offset + chunk.width <= chunk.wire->width' failed in kernel/rtlil.cc:3553.
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<benh> hrm... I think that's valid vhdl being translated into invalid verilog by ghdl-synth
<benh> and now
<benh> raised STORAGE_ERROR : stack overflow or erroneous memory access
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<benh> ah fixed with updated ghdl :)
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<ZipCPU> Glad you were able to figure it out!
<ZipCPU> Wow ... that was a response to a comment from ... yesterday? Wow. I need to pay more attention to these time stamps. ;)
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