Asu has quit [Read error: Connection reset by peer]
jakobwenzel has joined #yosys
captain_morgan4 has quit [Ping timeout: 258 seconds]
captain_morgan4 has joined #yosys
jeanthom has joined #yosys
futarisIRCcloud has quit [Quit: Connection closed for inactivity]
kraiskil has joined #yosys
gmc has joined #yosys
kraiskil has quit [Ping timeout: 260 seconds]
kraiskil has joined #yosys
kraiskil has quit [Ping timeout: 246 seconds]
peepsalot has quit [Ping timeout: 272 seconds]
Asuu has quit [Quit: Konversation terminated!]
craigo has quit [Ping timeout: 272 seconds]
Asu has joined #yosys
emeb has joined #yosys
kraiskil has joined #yosys
peepsalot has joined #yosys
futarisIRCcloud has joined #yosys
mirage335 has quit [Ping timeout: 272 seconds]
citypw has joined #yosys
mirage335 has joined #yosys
citypw has quit [Ping timeout: 240 seconds]
kgugala has quit [Ping timeout: 272 seconds]
Asuu has joined #yosys
Asu has quit [Read error: Connection reset by peer]
kraiskil has quit [Ping timeout: 246 seconds]
vidbina has joined #yosys
jakobwenzel has quit [Remote host closed the connection]
jeanthom has quit [Ping timeout: 272 seconds]
Asuu has quit [Remote host closed the connection]
Asu has joined #yosys
vidbina has quit [Ping timeout: 260 seconds]
FFY00 has quit [Remote host closed the connection]
FFY00 has joined #yosys
vidbina has joined #yosys
<Lofty>
ABC can take latches as input, right?
<daveshah>
I _think_ what abc call latches are actually flip-flops
<daveshah>
Maybe it supports real latches too though
<Lofty>
I was looking at the QuickLogic code and wondering if it would be more efficient to let ABC attempt to pack logic into latches
dys has quit [Ping timeout: 246 seconds]
<mwk>
Lofty: huh?
<mwk>
what do you mean by logic into latches?
<Lofty>
Imagine you have, say, a cone of logic with a latch and some other logic that fits inside a LUT
<Lofty>
What the QL flow does is map the latch manually
kgugala has joined #yosys
<Lofty>
Whereas the mapper could pack some of the logic into the LUT, reducing area
<mwk>
oh, like map latch into a LUT
<mwk>
that's a much more generic issue than just quicklogic though
<mwk>
like half our targets don't really support latches and they end up as logic
<Lofty>
That's why I asked if ABC could do it
<Lofty>
intel_alm doesn't presently map latches at all :P
<mwk>
which tbh I'd like to get rid of (as in, get rid of the current per-target way), and handle it in dfflegalize
<Lofty>
Sure
<mwk>
anyway I thought you were asking about something else with "pack logic into latches"
<mwk>
Xilinx has a fun mode where you can use a latch as an AND gate or as an OR gate
<Lofty>
Mmm
<mwk>
(which is of course very tricky to use efficiently because it involves turning *all* FFs in a slice into AND/OR gates, and good luck teaching synthesis to notice cases where it's worth it)
<mwk>
also I'm going to take a guess the timings for that gate are kinda shit
emeb has quit [Quit: Leaving.]
<Lofty>
Mmm
emeb_mac has joined #yosys
vidbina has quit [Ping timeout: 272 seconds]
az0re has quit [Remote host closed the connection]
futarisIRCcloud has quit [Quit: Connection closed for inactivity]
kraiskil has joined #yosys
SpaceCoaster has quit [Ping timeout: 272 seconds]
jakobwenzel has joined #yosys
kraiskil has quit [Ping timeout: 260 seconds]
az0re has joined #yosys
futarisIRCcloud has joined #yosys
<tnt>
So, can a (*whitebox*) module be top-level ? If I read_verilog one and then try 'show' it says "Nothing to show". If I remove the (*whitebox*) attrbiute, it works fine.
<tnt>
ok, bad example, 'show' fails on the working machine with the old yosys.
<tnt>
The real command is 'read_verilog ./symbiflow-arch-defs/quicklogic/primitives/logic/f_frag.sim.v; proc; cd F_FRAG; select F1 %co* o:* %i F1 %d'
<tnt>
which works on an "older" yosys (with the (*whitebox*) attr on F_FRAG module) and doesn't on a newer yosys ( I have to remove the whitebox attr )
X-Scale` has joined #yosys
X-Scale has quit [Ping timeout: 272 seconds]
X-Scale` is now known as X-Scale
X-Scale has quit [Ping timeout: 246 seconds]
X-Scale` has joined #yosys
X-Scale` is now known as X-Scale
jakobwenzel has quit [Quit: jakobwenzel]
N2TOH_ has joined #yosys
N2TOH has quit [Ping timeout: 260 seconds]
dys has joined #yosys
kuldeep has quit [Read error: Connection reset by peer]
sandeepkr has quit [Read error: Connection reset by peer]
indy_ is now known as indy
FFY00 has quit [Remote host closed the connection]
FFY00 has joined #yosys
FFY00 has quit [Remote host closed the connection]
dys has quit [Ping timeout: 246 seconds]
Asuu has joined #yosys
Asu has quit [Ping timeout: 272 seconds]
az0re has quit [Ping timeout: 240 seconds]
FFY00 has joined #yosys
Asuu has quit [Remote host closed the connection]
bzztploink has quit [Quit: Leaving]
X-Scale` has joined #yosys
X-Scale has quit [Ping timeout: 240 seconds]
X-Scale` is now known as X-Scale
bzztploink has joined #yosys
X-Scale` has joined #yosys
X-Scale has quit [Ping timeout: 272 seconds]
X-Scale` is now known as X-Scale
jmamish has joined #yosys
FFY00 has quit [Remote host closed the connection]
FFY00 has joined #yosys
craigo has joined #yosys
Cerpin has quit [Remote host closed the connection]