clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<solenskiner> Hello. I want to package the yosys suite for archlinux. I recently saw a seminar on youtube on the status for the project, and the speaker suggested to use head. Is that still true?
<whitequark> the 0.9 release is quite old and there have been significant improvements in HEAD
<whitequark> plus the netlists written by the 0.9 release are incompatible with nextpnr HEAD, I believe
<solenskiner> I'll use head then. Thanks!
<daveshah> Yes, this is one of the reasons why there hasn't been a release of nextpnr yet
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<lambda> solenskiner: what exactly do you want to package? yosys is in community, yosys-git is in the AUR...
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<solenskiner> Well, the whole suite, i guess: vtr, nexptr, trellis, etc. Thought that would be a good way to get familiarized with the parts, and since i'll be needing em anyways later... ¯\_(ツ)_/¯
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<daknig> maybe you wanna package symbiflow?
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<solenskiner> oh, yeah, i might have confused which part was like the umbrella project? sorry
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<daveshah> tbh nextpnr is more closely associated with yosys than symbiflow
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<lambda> solenskiner: might want to talk to FFY00, they have a bunch of those packages already.
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<ZirconiumX> The only really important bit of VTR is VPR, since there's a development effort to use it for Project X-Ray
<ZirconiumX> solenskiner: ^
<ZirconiumX> And I think they use a downstream for that
<daveshah> yeah, the symbiflow fork
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<FFY00> solenskiner, feel free to ping me if you need anything
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<strobokopp> Hi! I'm using nmigen+yosys to generate Verilog code that I synthesize with XST from Xilinx ISE. Now there's an issue when nmigen creates a switch with cases like this: case 1'0 and case 1'-
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<strobokopp> now the verilog output from yosys is casez() 1'h0 and 1'h? which XST does synthesize, but the result is wrong
<whitequark> strobokopp: hi
<whitequark> the verilog output from yosys looks correct to me
<whitequark> does XST synthesize correctly if you take that Verilog file and use 1'h1 in it instead, keeping everything else intact?
<strobokopp> whitequark: yes, then it works, I think. Let me double-check quickly..
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<strobokopp> example ilang code: https://pastebin.com/haEGUtf9 (switch \s_target is the one)
<tpb> Title: module\top wire width 1 input 0 \s_target wire width 2 input 1 \s_state - Pastebin.com (at pastebin.com)
<whitequark> strobokopp: actually, let's backtrack a bit. exactly which XST are you using? which device? is it one with the new parser?
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<strobokopp> whitequark: alright! it's XST from ISE 14.7, not sure where to find its own version number. Device is a Spartan-3E xc3s1600e.
<whitequark> are you passing `-use_new_parser yes` to XST?
<strobokopp> I never heard of that parser option :) so probably no, I'll check..
<strobokopp> whitequark: I wasn't, XST warns me now that I'm on my own with this, but the netlist actually looks correct now!
<whitequark> well, here you are. nmigen.build knows to pass this option automatically because otherwise xst uses a seriously noncompliant verilog parser
<ZirconiumX> Oh god, I've heard bad things about ISE, but this is terrifying
<strobokopp> oh well :D hours and hours of head-scratching over unexplainable behavior of the synthesized design and it's just that old parser, nmigen knew it all the time, I just didn't use it to call XST.
<whitequark> good luck with whatever it is you're using a S3E for...
<strobokopp> I knew I was in for trouble when I grabbed that Spartan 3 board fdrom the dumpster.
<whitequark> nmigen.build currently raises a NotImplementedError for 3E, but I think we can fix that if you're willing to put in some time testing it
<whitequark> I honestly thought I'll never see nmigen used for anything older than 3A
<whitequark> what's next, virtex-2? :
<whitequark> *:D
<strobokopp> hey you never know what you'll find in the junk, don't be suprised if I do show up again with sometrhing ancient!
<daveshah> xc2064 is where it is at!
<strobokopp> whitequark: but I could sure do some tests with the Spartan-3E to have support for it in nimgen
<ZirconiumX> I mean, we accidentally added support for the wrong Cyclone chip, WQ. I'm honestly surprised they're still fucking making EP3C
<whitequark> lol
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<daveshah> Big vendor FPGAs have pretty good longevity
<daveshah> I think Xilinx promise 20 years or something of that magnitude
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<daveshah> Heck, looks like Spartan 2 are still available to buy on DigiKey and not even flagged as obsolete
<whitequark> wow
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<ZirconiumX> The manual for the EP3C has a 1.0 release of March 2007.
<ZirconiumX> So yeah
<daveshah> Cyclone III is a bit special given that the arch lives on in a strange way
<daveshah> I think Cyclone IVE is pretty much a direct die shrink of it
<daveshah> and then that became 10LP
<strobokopp> ah and I'm pleased to see that there is also plenty of Spartan-3E supply on digikey. Virtex-II seems to be harder to find, having been discontinued in 2012 already! They really let us down there.
<strobokopp> oh wait, some Virtex-II Pro were only discontinued in 2018
<strobokopp> and then the rest (?) in February 2020
<daveshah> Still time for a last time buy!
<tpb> Title: XC2VP70-7FF1517C Xilinx Inc. | Integrated Circuits (ICs) | DigiKey (at www.digikey.co.uk)
<daveshah> Subject to mortgage approval at that price though
<strobokopp> needs better justification than trying to fix an old dev board to toy around with
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<strobokopp> whitequark: thanks, by the way. I don't think I would've had the will to look any further myself. I would've just blamed ISE and written a script to replace the question marks :D
<strobokopp> now I can still blame ISE, but in a somewhat educated manner
<whitequark> no problem, glad i could help
<whitequark> (don't tell anyone, but: i don't even use ISE. i just googled `"ISE" "casez" bug` and found a Xilinx AR recommending the option)
<strobokopp> smart!
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