<tux3>
Has anyone thought about rewriting the verilog frontend?
<tux3>
Every time I try to improve something and end up in simplify.cc, it makes me want to install <proprietary tool> :/
<awygle>
I am sure many people have _thought_ about it lol
<whitequark>
i believe rewriting the verilog frontend is very much encouraged
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<bubble_buster>
is verilator's frontend any good? it occurred to me a while ago that verilator has pretty complete synthesizable SV support, and it essentially "synthesizing" the input RTL, I wonder why that hasn't been mapped to yosys? licensing? or is it not as straightforward as I imagine?
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<awygle>
verilator is AL/GPL both of which are copyleft so i imagine that's an issue
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<awygle>
but also, probably it's not straightforward
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<tpb>
Title: Warning Options (Using the GNU Compiler Collection (GCC)) (at gcc.gnu.org)
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<ZirconiumX>
Unnecessary bikeshedding: Yosys is capitalised, but nextpnr is not, right?
<daveshah>
Yes
<ZirconiumX>
When did the JSON format change for nextpnr? I'm writing a mini-cookbook for Yosys etc and I think the format broke at some point
<ZirconiumX>
So I want to give a rough date for "your stuff is too old"
<ZirconiumX>
Since "master" or "latest" are not really valid versions :P
<daveshah>
I think the last change to affect ice40/ecp5 was around August 2019?
<ZirconiumX>
So 0.9?
<ZirconiumX>
Ish
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<awygle>
daveshah: are you open to taking something besides the JSON RTLIL representation as input to nextpnr? (ref. some discussions yesterday about RTLIL instability and LoFIRRTL)
<daveshah>
Post 0
<daveshah>
Post 0.9 release
<awygle>
(assuming somebody did the work, which, yknow, we're all busy lol)
<daveshah>
awygle: sure, although note that JSON is somewhat different to RTLIL
<daveshah>
But adding a new format shouldn't be too hard
<awygle>
oh? i thought it was just a representation of the RTLIL
<daveshah>
It is, but it is in a way that reduces the things that have compatability problems
<awygle>
(not to be confused with ilang, which iiuc is the [a] text representation of RTLIL)
<daveshah>
In particular it doesn't support processes
<daveshah>
The JSON spec also says new fields can be added and anything parsing has to ignore them
<awygle>
that's nice
<daveshah>
Although it has broken in the past, it should be pretty stable now
<daveshah>
That was due to a change in the way parameters are encoded
<ZirconiumX>
I'm wondering if `synth_ice40 -retime` should be recommended or not.
<ZirconiumX>
(currently I suggest `-dsp` for ultraplus)
<daveshah>
Definitely not, the current retiming is pretty horrible
<daveshah>
Its been rare to see a QoR improvement and it makes debugging harder if registers are messed with
<ZirconiumX>
Basically, I have four categories of options that aren't "default": useful (-top and -noflatten), sometimes useful (-dffe_min_ce_use if there's routing congestion, maybe?), worth mentioning (ABC9 for iCE40 might get better with time), and not worth mentioning (does anybody even use -nocarry?)
<daveshah>
nocarry is mostly useful if you think there is a bug related to carry chains
<ZirconiumX>
Or -nobram
<daveshah>
Ditto
<daveshah>
But not so much for ice40 where it will likely explode the design
<daveshah>
But for ECP5 I've forced everything into lutram to make sure a bug wasn't bram related
<ZirconiumX>
Sure, but if I'm mostly targeting somebody asking "what do these levers do?", I don't think it's important to mention them
<daveshah>
No
<daveshah>
Indeed not
<awygle>
2c, i'd want you to mention them and say "these are for debugging, not for production use, here's what they do", because otherwise i'd be like "hey wait these show up in -help but you don't mention them! is this article out of date?!"
<awygle>
but i may be atypical
<ZirconiumX>
Okay, valid point
<awygle>
btw why does yosys use single - instead of double -- ? this always annoys me when i encounter it :(
<ZirconiumX>
Conversely it always annoys me when I have to use -- for nextpnr :P
<whitequark>
yosys passes aren't unixy tools
<whitequark>
i guess that's why
<daveshah>
Vivado tcl commands, for example use single dash too, iirc
<ZirconiumX>
Likewise for Quartus I think
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<ZirconiumX>
Is -edif for icecube or something?
<ZirconiumX>
(in synth_ice40)
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<ZirconiumX>
daveshah: ^
<daknig>
what's the status of yosys regarding to the support of the 7 series? what features are missing?
<daknig>
I am new to FPGAs and I was thinking of using yosys for my project , but it requires the DDR memory on my zynq and DSP slices (as well as other things)
<ZirconiumX>
I think shift-register inference is not quite there yet