clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<Geza> az0re: Thanks for the confirmation. My constraints are various but fall into a small number of categories, some of them are either present or not per test (e.g.: if there is a reset, is it active high, is it active low?) the others depend on the interface of the top level in the test (e.g.: constraints on flow-control signals), which can be
<Geza> arbitrary, so I think doing my own miters is probably the best.
<az0re> Yup makes sense to me.
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<ZirconiumX> dh73: could you please work on #2007 (the MIF generator)? Not having support for initialised RAM is pretty crippling for both synth_intel and synth_intel_alm
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