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<ashfaq1717>
hi all
<ashfaq1717>
I'm doing synthesization of Single Cycle RISCV Processor, when I synthesize top module of processor, I have a problem when run 'hierarchy -check' command, I get error this ALU, (ALU instantiation) is not part of the design. This error comes for all instantiations....Can somebody help me, why is it?
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<ZipCPU>
ashfaq1717: You need to read the verilog files for the rest of the design into Yosys. Typically, this is done via the "read_verilog" command, although I kind of like using "read -sv filename.v" myself.
<ZirconiumX>
Or pass them on the command line
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<Forty-Bot>
does verilator support +: in declarations?
<Forty-Bot>
e.g. something like "wire [0 +: 32] foo;"
<Forty-Bot>
I can use that syntax fine in yosys, and it seems to be allowed by the standard
<Forty-Bot>
but verilator gives a syntax error
<Forty-Bot>
am I missing some kind of compiler option?
<whitequark>
Forty-Bot: doesn't seem to be allowed per 1364
<Forty-Bot>
ok, so I'm looking at 1364-2005 on page 504-505 and +: is defined as a valid constant_range_expression
<whitequark>
yes but a type declaration uses a `range`, not a `constant_range_expression`
<Forty-Bot>
then on page 506, a net_lvalue is defined as an identifier plus a constant_range_expression
<Forty-Bot>
is that just for assign?
<whitequark>
yes
<whitequark>
that's what an lvalue is: a value on lhs of assignment
<Forty-Bot>
ah, ok thanks
<Forty-Bot>
it's kinda strange that it's not allowed for declarations
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<whitequark>
what would that mean for declarations?
<Forty-Bot>
the same thing it means for l-values?
<whitequark>
oh, i see what you mean
<whitequark>
or rather why you want it
<whitequark>
that seems inconsistent syntactically
<Forty-Bot>
yes
<whitequark>
no, i mean, being able to use :+ seems
<whitequark>
from my point of view, but i also see yours
<Forty-Bot>
the real issue, is if you want to have "one true range-specifier" it has to be :
<Forty-Bot>
and : can be rather unweildy for certain expressions
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<whitequark>
ahhh
<whitequark>
ok, that makes sense
<Forty-Bot>
another example, say I have two variables which are WIDTH wide, and I want to add them
<Forty-Bot>
the result will be WIDTH + 1 wide, but specifying it like "wire [WIDTH:0] sum"... almost looks like a typo
<Forty-Bot>
whereas "wire [0 +: WIDTH + 1] sum" is obviously supposed to be WIDTH + 1 wide