clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<awygle> are there any good examples of throughput-based formal properties?
<awygle> trying to phrase the requirement "assuming a sink which tries to read every cycle, this core's sink must be able to accept one transaction every clock cycle unless [list of exceptions]"
<awygle> and i can't really figure out how to do that...
<awygle> i guess i can do a cover trace fairly easily actually
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<az0re> Do you have a signal for "able to accept a transaction"?
<az0re> then it should be not(redor(exception_bitvector)) -> able_to_accept_transaction, no?
<az0re> so "or(not(redor(exception_bitvector)), able_to_accept_transaction)"
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<sensille> when yosys infers BRAM, it rejects a lot of my smallish register banks with "min efficiency 5' not met (ECP5)
<sensille> is that only not to waste bram, or also that the overhead to use the bram would be similar to not using it at all?
<sensille> (and others again get rejected with "Read port #0 is in clock domain !~async~.")
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<ZirconiumX> sensille: it's to not waste BRAM, but there needs to be a better heuristic for it all
<ZirconiumX> I think it will favour LUTRAM for it though
<ZirconiumX> sensille: (and others again get rejected with "Read port #0 is in clock domain !~async~.") <--- the ECP5 has synchronous read, but you're asking for asynchronous read, for which it would use LUTRAM.
<sensille> yeah, some get caught by DPR16X4 later on
<sensille> i can't find the async read though, the output is explicitly registered
<ZirconiumX> Generally you want BRAM for deep but narrow memories, and LUTRAM for wide but shallow memories
<ZirconiumX> Can I see your Verilog module for it?
<tpb> Title: conan_fpga/fifo.v at master · sensille/conan_fpga · GitHub (at github.com)
<sensille> for the async read warning
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<ZirconiumX> sensille: can you give the exact module path of the thing you want inferred as BRAM?
<ZirconiumX> Like, conan.u_command.u_stepper.genstepdir[0].u_stepdir.u_fifo.ram
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<ZirconiumX> Since as far as I can tell, the async read thing isn't actually a warning
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<sensille> ZirconiumX: conan.u_framing.recv_ring for example
<sensille> and conan.u_framing.send_ring
<ZirconiumX> The error is actually this: Bram port B1.1 has incompatible clock type.
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<ZirconiumX> By the way, you don't need to bother with `verilog -defer` if you use sensible defaults
<ZirconiumX> daveshah: can you take a look at this?
<daveshah> Are you initialising or resetting the output register?
<ZirconiumX> Doesn't look like it
<daveshah> I can have a look later
<sensille> indeed, "Bram port B1.1 has incompatible clock type." is in the next line
<sensille> at least my intention is that everything is driven by the one and only clk
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<daveshah> With data width 8, address width 12, that file infers memory fine for me
<ZirconiumX> The params used are data width 6 address width 5
<daveshah> Oh, then yes it seems to fail efficiency criterea
<sensille> efficiency=22
<tpb> Title: Processing conan.u_framing.recv_ring: Properties: ports=2 bits=4096 rports=1 - Pastebin.com (at pastebin.com)
<daveshah> Oh, not the FIFO module
<sensille> it is probably how i use the fifo module
<sensille> it is an instance of the fifo module
<ZirconiumX> > reg [7:0] recv_ring [RING_SIZE-1:0];
<ZirconiumX> No, it's not
<daveshah> That looks like an async port?
<tpb> Title: conan_fpga/framing.v at master · sensille/conan_fpga · GitHub (at github.com)
* sensille blushes with shame
<sensille> ZirconiumX, daveshah: sorry, i don't know where i got the idea from it's the fifo. the fifo just fails the efficiency test
<sensille> thanks for looking at this
<ZirconiumX> No, I'm looking through the FIFO mappings, and it seems like all of them pass the efficiency test at 92%
<daveshah> I think it would actually have mapped (as a transparent port, with the reg on the address) without the '= 0' here: https://github.com/sensille/conan_fpga/blob/master/framing.v#L83
<tpb> Title: conan_fpga/framing.v at master · sensille/conan_fpga · GitHub (at github.com)
<sensille> conan.u_framing.send_len_fifo.ram fails with 1%
<sensille> why is initializing the rptr a problem?
<ZirconiumX> Because Yosys can't merge flops into memories at the moment
<sensille> i guess i could initialize rptr with the first clk
<sensille> alternatively i need to register the output?
<ZirconiumX> You already have a clear option to initialise rptr
<ZirconiumX> Really though, I don't know much about memories here
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